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[profcheck] Disable verification of selects on vector conditions. #167973

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Merged
merged 1 commit into from
Nov 14, 2025
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[profcheck] Disable verification of selects on vector conditions. #167973

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16 changes: 10 additions & 6 deletions llvm/lib/Transforms/Utils/ProfileVerify.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,9 +102,11 @@ bool ProfileInjector::inject() {
for (auto &BB : F) {
if (AnnotateSelect) {
for (auto &I : BB) {
if (isa<SelectInst>(I) && !I.getMetadata(LLVMContext::MD_prof))
setBranchWeights(I, {SelectTrueWeight, SelectFalseWeight},
/*IsExpected=*/false);
if (auto *SI = dyn_cast<SelectInst>(&I))
if (!SI->getCondition()->getType()->isVectorTy() &&
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@boomanaiden154 boomanaiden154 Nov 14, 2025

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Probably more readable if we have a if (!SI->...->isVectorTy() { continue; }.

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@mtrofin mtrofin Nov 14, 2025 •
edited
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would need more instructions, what am I missing.

!I.getMetadata(LLVMContext::MD_prof))
setBranchWeights(I, {SelectTrueWeight, SelectFalseWeight},
/*IsExpected=*/false);
}
}
auto *Term = getTerminatorBenefitingFromMDProf(BB);
Expand Down Expand Up @@ -185,9 +187,11 @@ PreservedAnalyses ProfileVerifierPass::run(Function &F,
for (const auto &BB : F) {
if (AnnotateSelect) {
for (const auto &I : BB)
if (isa<SelectInst>(I) && !I.getMetadata(LLVMContext::MD_prof))
F.getContext().emitError(
"Profile verification failed: select annotation missing");
if (auto *SI = dyn_cast<SelectInst>(&I))
if (!SI->getCondition()->getType()->isVectorTy() &&
!I.getMetadata(LLVMContext::MD_prof))
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@boomanaiden154 boomanaiden154 Nov 14, 2025

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Same here.

F.getContext().emitError(
"Profile verification failed: select annotation missing");
}
if (const auto *Term =
ProfileInjector::getTerminatorBenefitingFromMDProf(BB))
Expand Down
22 changes: 20 additions & 2 deletions llvm/test/Transforms/PGOProfile/profcheck-select.ll
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Expand Up @@ -15,7 +15,11 @@
; RUN: not opt -passes=prof-verify %t/verify-missing.ll 2>&1 | FileCheck %t/verify-missing.ll

; verify we can disable it. It's sufficient to see opt not failing.
; RUN: opt -passes=prof-verify -profcheck-annotate-select=0 %t/verify-missing.ll
; RUN: opt -passes=prof-verify -profcheck-annotate-select=0 --disable-output %t/verify-missing.ll
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@boomanaiden154 boomanaiden154 Nov 14, 2025

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Why are we disabling output? It should just go nowhere.

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@mtrofin mtrofin Nov 14, 2025

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when you run the lit test at the command line, it gets printed out.


; verify vector selects without profiles are OK. It's sufficient opt doesn't fail.
; RUN: opt -passes=prof-verify --disable-output %t/verify-vec.ll


;--- inject.ll
declare void @foo(i32 %a);
Expand All @@ -24,8 +28,16 @@ define void @bar(i1 %c) {
call void @foo(i32 %v)
ret void
}

define <2 x i32> @vec(<2 x i1> %c, <2 x i32> %v1, <2 x i32> %v2) {
%r = select <2 x i1> %c, <2 x i32> %v1, <2 x i32> %v2
ret <2 x i32> %r
}

; CHECK-LABEL: @bar
; CHECK: %v = select i1 %c, i32 1, i32 2, !prof !1
; CHECK-LABEL: @vec
; CHECK-NOT: select {{.*}} !prof
; CHECK: !0 = !{!"function_entry_count", i64 1000}
; CHECK: !1 = !{!"branch_weights", i32 2, i32 3}

Expand Down Expand Up @@ -64,4 +76,10 @@ define void @bar(i1 %c) !prof !0 {
ret void
}
!0 = !{!"function_entry_count", i64 1000}
; CHECK: Profile verification failed: select annotation missing
; CHECK: Profile verification failed: select annotation missing

;--- verify-vec.ll
define <2 x i32> @vec(<2 x i1> %c, <2 x i32> %v1, <2 x i32> %v2) !prof !{!"function_entry_count", i32 10} {
%r = select <2 x i1> %c, <2 x i32> %v1, <2 x i32> %v2
ret <2 x i32> %r
}
30 changes: 0 additions & 30 deletions llvm/utils/profcheck-xfail.txt
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Expand Up @@ -24,7 +24,6 @@ DebugInfo/Generic/block-asan.ll
DebugInfo/X86/asan_debug_info.ll
LTO/X86/diagnostic-handler-remarks-with-hotness.ll
Other/optimization-remarks-auto.ll
Other/X86/debugcounter-partiallyinlinelibcalls.ll
Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
Transforms/AtomicExpand/SPARC/partword.ll
Transforms/Attributor/align.ll
Expand Down Expand Up @@ -94,8 +93,6 @@ Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll
Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll
Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll
Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll
Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
Transforms/CodeGenPrepare/X86/vec-shift.ll
Transforms/Coroutines/coro-await-suspend-lower-invoke.ll
Transforms/Coroutines/coro-await-suspend-lower.ll
Transforms/Coroutines/coro-byval-param.ll
Expand Down Expand Up @@ -182,8 +179,6 @@ Transforms/GlobalOpt/shrink-global-to-bool-check-debug.ll
Transforms/GlobalOpt/shrink-global-to-bool-opaque-ptrs.ll
Transforms/GVN/debugloc-load-select.ll
Transforms/GVN/load-through-select-dbg.ll
Transforms/GVN/masked-load-store.ll
Transforms/GVN/masked-load-store-no-mem-dep.ll
Transforms/GVN/opaque-ptr.ll
Transforms/GVN/pr69301.ll
Transforms/GVN/pre-invalid-prof-metadata.ll
Expand Down Expand Up @@ -236,9 +231,6 @@ Transforms/IndVarSimplify/pr45835.ll
Transforms/IndVarSimplify/preserving-debugloc-rem-div.ll
Transforms/InstCombine/2004-09-20-BadLoadCombine.ll
Transforms/InstCombine/2005-04-07-UDivSelectCrash.ll
Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll
Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll
Transforms/InstCombine/AArch64/sve-intrinsic-simplify-shift.ll
Transforms/InstCombine/add-mask.ll
Transforms/InstCombine/add-shl-mul-umax.ll
Transforms/InstCombine/and2.ll
Expand Down Expand Up @@ -274,7 +266,6 @@ Transforms/InstCombine/fmul-bool.ll
Transforms/InstCombine/fmul.ll
Transforms/InstCombine/fneg.ll
Transforms/InstCombine/fold-ctpop-of-not.ll
Transforms/InstCombine/fold-ext-eq-c-with-op.ll
Transforms/InstCombine/free-inversion.ll
Transforms/InstCombine/icmp-and-lowbit-mask.ll
Transforms/InstCombine/icmp.ll
Expand All @@ -294,8 +285,6 @@ Transforms/InstCombine/loadstore-metadata.ll
Transforms/InstCombine/logical-select-inseltpoison.ll
Transforms/InstCombine/logical-select.ll
Transforms/InstCombine/lshr.ll
Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
Transforms/InstCombine/masked_intrinsics.ll
Transforms/InstCombine/memchr-11.ll
Transforms/InstCombine/memchr-2.ll
Transforms/InstCombine/memchr-3.ll
Expand Down Expand Up @@ -332,14 +321,11 @@ Transforms/InstCombine/select-and-or.ll
Transforms/InstCombine/select-cmp-br.ll
Transforms/InstCombine/select-cmp.ll
Transforms/InstCombine/select-factorize.ll
Transforms/InstCombine/select_frexp.ll
Transforms/InstCombine/select.ll
Transforms/InstCombine/select-min-max.ll
Transforms/InstCombine/select-of-symmetric-selects.ll
Transforms/InstCombine/select-select.ll
Transforms/InstCombine/shift.ll
Transforms/InstCombine/shuffle-select-narrow-inseltpoison.ll
Transforms/InstCombine/shuffle-select-narrow.ll
Transforms/InstCombine/simplify-demanded-fpclass.ll
Transforms/InstCombine/sink-not-into-another-hand-of-logical-and.ll
Transforms/InstCombine/sink-not-into-another-hand-of-logical-or.ll
Expand All @@ -355,11 +341,8 @@ Transforms/InstCombine/sub-xor-cmp.ll
Transforms/InstCombine/truncating-saturate.ll
Transforms/InstCombine/unordered-fcmp-select.ll
Transforms/InstCombine/urem-via-cmp-select.ll
Transforms/InstCombine/vec_sext.ll
Transforms/InstCombine/vector-urem.ll
Transforms/InstCombine/wcslen-1.ll
Transforms/InstCombine/wcslen-3.ll
Transforms/InstCombine/X86/blend_x86.ll
Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
Transforms/InstCombine/X86/x86-avx512.ll
Transforms/InstCombine/xor-and-or.ll
Expand Down Expand Up @@ -607,36 +590,25 @@ Transforms/OpenMP/spmdization_indirect.ll
Transforms/OpenMP/spmdization.ll
Transforms/OpenMP/spmdization_no_guarding_two_reaching_kernels.ll
Transforms/OpenMP/spmdization_remarks.ll
Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll
Transforms/PGOProfile/comdat.ll
Transforms/PGOProfile/memop_profile_funclet_wasm.ll
Transforms/PGOProfile/X86/macho.ll
Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
Transforms/PhaseOrdering/AArch64/predicated-reduction.ll
Transforms/PhaseOrdering/AArch64/quant_4x4.ll
Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
Transforms/PhaseOrdering/vector-select.ll
Transforms/PhaseOrdering/X86/blendv-select.ll
Transforms/PhaseOrdering/X86/merge-functions2.ll
Transforms/PhaseOrdering/X86/merge-functions3.ll
Transforms/PhaseOrdering/X86/merge-functions.ll
Transforms/PhaseOrdering/X86/pr52078.ll
Transforms/PhaseOrdering/X86/pr67803.ll
Transforms/PhaseOrdering/X86/preserve-access-group.ll
Transforms/PhaseOrdering/X86/vector-reductions.ll
Transforms/PreISelIntrinsicLowering/AArch64/expand-exp.ll
Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
Transforms/PreISelIntrinsicLowering/expand-vp.ll
Transforms/PreISelIntrinsicLowering/PowerPC/memset-pattern.ll
Transforms/PreISelIntrinsicLowering/RISCV/memset-pattern.ll
Transforms/PreISelIntrinsicLowering/X86/memcpy-inline-non-constant-len.ll
Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll
Transforms/PreISelIntrinsicLowering/X86/memset-pattern.ll
Transforms/SampleProfile/pseudo-probe-profile-mismatch-thinlto.ll
Transforms/SampleProfile/remarks-hotness.ll
Transforms/SandboxVectorizer/special_opcodes.ll
Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-load.ll
Transforms/ScalarizeMaskedMemIntrin/AArch64/expand-masked-store.ll
Transforms/ScalarizeMaskedMemIntrin/AArch64/streaming-compatible-expand-masked-gather-scatter.ll
Expand Down Expand Up @@ -675,5 +647,3 @@ Transforms/UnifyLoopExits/switch.ll
Transforms/UnifyLoopExits/undef-phis.ll
Transforms/Util/libcalls-opt-remarks.ll
Transforms/Util/lowerswitch.ll
Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Transforms/VectorCombine/X86/shuffle-of-selects.ll
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