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Updates canCreateUndefOrPoison to return a precise result for ISD::VECTOR_COMPRESS, correctly reporting that it generates undef (in the tail) but not poison.

Fixes #167710

@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Nov 14, 2025
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llvmbot commented Nov 14, 2025

@llvm/pr-subscribers-backend-x86

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Author: 陈子昂 (Michael-Chen-NJU)

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Updates canCreateUndefOrPoison to return a precise result for ISD::VECTOR_COMPRESS, correctly reporting that it generates undef (in the tail) but not poison.

Fixes #167710


Full diff: https://github.com/llvm/llvm-project/pull/168010.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+5)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c2b4c19846316..38fee7c83e1c0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5702,6 +5702,11 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
     return false;
   }
 
+  case ISD::VECTOR_COMPRESS:
+    // Return true only if undef is checked and at least one element is
+    // demanded.
+    return !PoisonOnly && !DemandedElts.isZero();
+
   default:
     // Allow the target to implement this method for its nodes.
     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||

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Needs tests

@RKSimon RKSimon self-requested a review November 14, 2025 13:35
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RKSimon commented Nov 14, 2025

@Michael-Chen-NJU You'll probably have to do value tracking style tests:

declare <16 x i32> @llvm.experimental.vector.compress.v16i32(<16 x i32>, <16 x i1>, <16 x i32>)

define <16 x i32> @src(<16 x i32> %a0, <16 x i32> %a1, <16 x i8> %a3) {
  %cmp = icmp sgt <16 x i32> %a0, %a1
  %ext = zext <16 x i8> %a3 to <16 x i32>
  %cpr = call <16 x i32> @llvm.experimental.vector.compress.v16i32(<16 x i32> %ext, <16 x i1> %cmp, <16 x i32> splat(i32 15))
  %fr = freeze <16 x i32> %cpr
  %and = and <16 x i32> %fr, splat (i32 15)
  ret <16 x i32> %and
}

define <16 x i32> @tgt(<16 x i32> %a0, <16 x i32> %a1, <16 x i8> %a3) {
  %cmp = icmp sgt <16 x i32> %a0, %a1
  %ext = zext <16 x i8> %a3 to <16 x i32>
  %cpr = call <16 x i32> @llvm.experimental.vector.compress.v16i32(<16 x i32> %ext, <16 x i1> %cmp, <16 x i32> splat(i32 15))
  %and = and <16 x i32> %cpr, splat (i32 255)
  ret <16 x i32> %and
}

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github-actions bot commented Nov 17, 2025

✅ With the latest revision this PR passed the undef deprecator.

@Michael-Chen-NJU Michael-Chen-NJU force-pushed the fix-167710-vector-compress branch from 122d49a to d67fee9 Compare November 17, 2025 16:03
@RKSimon RKSimon self-requested a review November 17, 2025 16:48
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🐧 Linux x64 Test Results

  • 186293 tests passed
  • 4853 tests skipped

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LGTM

@RKSimon RKSimon enabled auto-merge (squash) November 19, 2025 09:56
@RKSimon RKSimon merged commit e38529d into llvm:main Nov 19, 2025
9 of 10 checks passed
@Michael-Chen-NJU Michael-Chen-NJU deleted the fix-167710-vector-compress branch November 20, 2025 03:24
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[DAG] canCreateUndefOrPoison - add ISD::VECTOR_COMPRESS handling

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