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[ARM] Remove Subtarget from ARMAsmPrinter #168264

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[ARM] Remove Subtarget from ARMAsmPrinter #168264

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8bdb32e
[ARM] Remove Subtarget from ARMAsmPrinter
davemgreen Nov 16, 2025
5b4bdbf
Move isROPI and isRWPI back to Subtarget and add a FIXME about them b…
davemgreen Nov 25, 2025
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47 changes: 21 additions & 26 deletions llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -51,8 +51,8 @@ using namespace llvm;

ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer), ID), Subtarget(nullptr), AFI(nullptr),
MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
: AsmPrinter(TM, std::move(Streamer), ID), AFI(nullptr), MCP(nullptr),
InConstantPool(false), OptimizationGoals(-1) {}

const ARMBaseTargetMachine &ARMAsmPrinter::getTM() const {
return static_cast<const ARMBaseTargetMachine &>(TM);
Expand Down Expand Up @@ -116,7 +116,6 @@ void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
AFI = MF.getInfo<ARMFunctionInfo>();
MCP = MF.getConstantPool();
Subtarget = &MF.getSubtarget<ARMSubtarget>();

SetupMachineFunction(MF);
const Function &F = MF.getFunction();
Expand Down Expand Up @@ -154,7 +153,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
OptimizationGoals = 0;

if (Subtarget->isTargetCOFF()) {
if (TM.getTargetTriple().isOSBinFormatCOFF()) {
bool Local = F.hasLocalLinkage();
COFF::SymbolStorageClass Scl =
Local ? COFF::IMAGE_SYM_CLASS_STATIC : COFF::IMAGE_SYM_CLASS_EXTERNAL;
Expand Down Expand Up @@ -260,8 +259,8 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
break;
}
case MachineOperand::MO_ConstantPoolIndex:
if (Subtarget->genExecuteOnly())
llvm_unreachable("execute-only should not generate constant pools");
assert(!MF->getSubtarget<ARMSubtarget>().genExecuteOnly() &&
"execute-only should not generate constant pools");
GetCPISymbol(MO.getIndex())->print(O, MAI);
break;
}
Expand Down Expand Up @@ -1048,7 +1047,8 @@ void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) {
// .word (LBB1 - LJTI_0_0)
const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);

if (isPositionIndependent() || Subtarget->isROPI())
const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
if (isPositionIndependent() || STI.isROPI())
Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
OutContext),
OutContext);
Expand Down Expand Up @@ -1097,7 +1097,8 @@ void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
const MachineOperand &MO1 = MI->getOperand(1);
unsigned JTI = MO1.getIndex();

if (Subtarget->isThumb1Only())
const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
if (STI.isThumb1Only())
emitAlignment(Align(4));

MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
Expand Down Expand Up @@ -1905,6 +1906,7 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
ARM_MC::verifyInstructionPredicates(MI->getOpcode(),
getSubtargetInfo().getFeatureBits());

const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
const DataLayout &DL = getDataLayout();
MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
Expand All @@ -1916,8 +1918,8 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
}

// Emit unwinding stuff for frame-related instructions
if (Subtarget->isTargetEHABICompatible() &&
MI->getFlag(MachineInstr::FrameSetup))
if (TM.getTargetTriple().isTargetEHABICompatible() &&
MI->getFlag(MachineInstr::FrameSetup))
EmitUnwindingInstruction(MI);

// Do any auto-generated pseudo lowerings.
Expand Down Expand Up @@ -1983,14 +1985,13 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
// Add 's' bit operand (always reg0 for this)
.addReg(0));

assert(Subtarget->hasV4TOps());
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
.addReg(MI->getOperand(0).getReg()));
assert(STI.hasV4TOps() && "Expected V4TOps for BX call");
EmitToStreamer(*OutStreamer,
MCInstBuilder(ARM::BX).addReg(MI->getOperand(0).getReg()));
return;
}
case ARM::tBX_CALL: {
if (Subtarget->hasV5TOps())
llvm_unreachable("Expected BLX to be selected for v5t+");
assert(!STI.hasV5TOps() && "Expected BLX to be selected for v5t+");

// On ARM v4t, when doing a call from thumb mode, we need to ensure
// that the saved lr has its LSB set correctly (the arch doesn't
Expand Down Expand Up @@ -2279,8 +2280,8 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
return;
}
case ARM::CONSTPOOL_ENTRY: {
if (Subtarget->genExecuteOnly())
llvm_unreachable("execute-only should not generate constant pools");
assert(!STI.genExecuteOnly() &&
"execute-only should not generate constant pools");

/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
/// in the function. The first operand is the ID# for this instruction, the
Expand Down Expand Up @@ -2486,7 +2487,7 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
case ARM::TRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
if (!Subtarget->isTargetMachO()) {
if (!TM.getTargetTriple().isOSBinFormatMachO()) {
uint32_t Val = 0xe7ffdefeUL;
OutStreamer->AddComment("trap");
ATS.emitInst(Val);
Expand All @@ -2497,7 +2498,7 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
case ARM::tTRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
if (!Subtarget->isTargetMachO()) {
if (!TM.getTargetTriple().isOSBinFormatMachO()) {
uint16_t Val = 0xdefe;
OutStreamer->AddComment("trap");
ATS.emitInst(Val, 'n');
Expand Down Expand Up @@ -2657,9 +2658,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addImm(ARMCC::AL)
.addReg(0));

const MachineFunction &MF = *MI->getParent()->getParent();
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();

if (STI.isTargetDarwin() || STI.isTargetWindows()) {
// These platforms always use the same frame register
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
Expand Down Expand Up @@ -2688,7 +2686,7 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
.addReg(0));
}

assert(Subtarget->hasV4TOps());
assert(STI.hasV4TOps());
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
.addReg(ScratchReg)
// Predicate.
Expand All @@ -2705,9 +2703,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
Register SrcReg = MI->getOperand(0).getReg();
Register ScratchReg = MI->getOperand(1).getReg();

const MachineFunction &MF = *MI->getParent()->getParent();
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();

EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
.addReg(ScratchReg)
.addReg(SrcReg)
Expand Down
6 changes: 1 addition & 5 deletions llvm/lib/Target/ARM/ARMAsmPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,13 @@
#ifndef LLVM_LIB_TARGET_ARM_ARMASMPRINTER_H
#define LLVM_LIB_TARGET_ARM_ARMASMPRINTER_H

#include "ARMSubtarget.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/Target/TargetMachine.h"

namespace llvm {

class ARMFunctionInfo;
class ARMBaseTargetMachine;
class MCOperand;
class MachineConstantPool;
class MachineOperand;
Expand All @@ -33,10 +33,6 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter {
static char ID;

private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when printing asm code for different targets.
const ARMSubtarget *Subtarget;

/// AFI - Keep a pointer to ARMFunctionInfo for the current
/// MachineFunction.
ARMFunctionInfo *AFI;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMMCInstLower.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -112,8 +112,8 @@ bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
break;
case MachineOperand::MO_ConstantPoolIndex:
if (Subtarget->genExecuteOnly())
llvm_unreachable("execute-only should not generate constant pools");
assert(!MF->getSubtarget<ARMSubtarget>().genExecuteOnly() &&
"execute-only should not generate constant pools");
MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
break;
case MachineOperand::MO_BlockAddress:
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/ARM/ARMSubtarget.cpp
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Expand Up @@ -309,10 +309,15 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
}

bool ARMSubtarget::isROPI() const {
// FIXME: This should ideally come from a function attribute, to work
// correctly with LTO.
return TM.getRelocationModel() == Reloc::ROPI ||
TM.getRelocationModel() == Reloc::ROPI_RWPI;
}

bool ARMSubtarget::isRWPI() const {
// FIXME: This should ideally come from a function attribute, to work
// correctly with LTO.
return TM.getRelocationModel() == Reloc::RWPI ||
TM.getRelocationModel() == Reloc::ROPI_RWPI;
}
Expand Down