Skip to content

[VPlan] Fix OpType-mismatch in getFlagsFromIndDesc #168560

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Nov 18, 2025
Merged

[VPlan] Fix OpType-mismatch in getFlagsFromIndDesc #168560

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
75f844d
[LV] Pre-commit crashing induction-wrapflags test
artagnon Nov 18, 2025
7eb1da3
[VPlan] Fix OpType-mismatch in getFlagsFromIndDesc
artagnon Nov 18, 2025
41ce479
[LV] NFC test improvement
artagnon Nov 18, 2025
55b13f1
[VPlan] Add assert
artagnon Nov 18, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 4 additions & 1 deletion llvm/lib/Transforms/Vectorize/VPlanUtils.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,10 @@ inline VPIRFlags getFlagsFromIndDesc(const InductionDescriptor &ID) {
ID.getInductionBinOp()))
return VPIRFlags::WrapFlagsTy(OBO->hasNoUnsignedWrap(),
OBO->hasNoSignedWrap());
return {};

assert(ID.getKind() == InductionDescriptor::IK_IntInduction &&
"Expected int induction");
return VPIRFlags::WrapFlagsTy(false, false);
}
} // namespace vputils

Expand Down
70 changes: 70 additions & 0 deletions llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph" --version 6
; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s

define void @induction_with_multiple_instructions_in_chain(ptr %p, ptr noalias %q) {
; CHECK-LABEL: define void @induction_with_multiple_instructions_in_chain(
; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 3, i32 6, i32 9, i32 12>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <4 x i32> [ <i32 0, i32 3, i32 6, i32 9>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = sext <4 x i32> [[VEC_IND]] to <4 x i64>
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i32 2
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP0]], i32 3
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]]
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP4]]
; CHECK-NEXT: store i8 0, ptr [[TMP5]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP8]], align 1
; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i32> [[VEC_IND1]] to <4 x i64>
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i32 0
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i64> [[TMP9]], i32 1
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP10]]
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP11]]
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP12]]
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP13]]
; CHECK-NEXT: store i8 0, ptr [[TMP14]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP15]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP16]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP17]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 12)
; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <4 x i32> [[VEC_IND1]], splat (i32 12)
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
; CHECK: [[SCALAR_PH]]:
;
entry:
br label %loop

loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%ind.1 = phi i32 [ 3, %entry ], [ %ind.1.next, %loop ]
%ind.2 = phi i32 [ 0, %entry ], [ %ind.1, %loop ]
%sext.1 = sext i32 %ind.1 to i64
%gep.1 = getelementptr i8, ptr %p, i64 %sext.1
store i8 0, ptr %gep.1
%sext.2 = sext i32 %ind.2 to i64
%gep.2 = getelementptr i8, ptr %q, i64 %sext.2
store i8 0, ptr %gep.2
%iv.next = add i64 %iv, 1
%ind.1.next = add i32 %ind.1, 3
%ec = icmp eq i64 %iv, 1024
br i1 %ec, label %exit, label %loop

exit:
ret void
}
Loading