CodeGen: Add subtarget to TargetLoweringBase constructor #168620
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Currently LibcallLoweringInfo is defined inside of TargetLowering, which is owned by the subtarget. Pass in the subtarget so we can construct LibcallLoweringInfo with the subtarget. This is a temporary step that should be revertable in the future, after LibcallLoweringInfo is moved out of TargetLowering.
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This was referenced Nov 18, 2025
arsenm
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MacDue,
aeubanks,
cdevadas,
compnerd,
dpaoliello,
efriedma-quic,
frederik-h,
mstorsjo,
paperchalice,
rnk,
sdesmalen-arm,
shiltian,
smithp35 and
vikramRH
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This change should be good by itself, TLI implementations generally need subtarget to guide lowering decisions etc. |
🐧 Linux x64 Test Results
|
llvmbot
added
backend:Sparc
backend:SystemZ
backend:WebAssembly
backend:X86
backend:DirectX
backend:SPIR-V
backend:NVPTX
backend:loongarch
llvm:SelectionDAG
Member
|
@llvm/pr-subscribers-backend-msp430 @llvm/pr-subscribers-backend-aarch64 Author: Matt Arsenault (arsenm) ChangesCurrently LibcallLoweringInfo is defined inside of TargetLowering, Patch is 25.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168620.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c932c523e423..7df5d8a09f0f6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -355,7 +355,8 @@ class LLVM_ABI TargetLoweringBase {
llvm_unreachable("Invalid content kind");
}
- explicit TargetLoweringBase(const TargetMachine &TM);
+ explicit TargetLoweringBase(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase();
@@ -3977,7 +3978,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
+ explicit TargetLowering(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
~TargetLowering() override;
bool isPositionIndependent() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb64f4ee70280..a2c6a22043001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -41,8 +41,9 @@ using namespace llvm;
using namespace llvm::SDPatternMatch;
/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
- : TargetLoweringBase(tm) {}
+TargetLowering::TargetLowering(const TargetMachine &tm,
+ const TargetSubtargetInfo &sti)
+ : TargetLoweringBase(tm, sti) {}
// Define the virtual destructor out-of-line for build efficiency.
TargetLowering::~TargetLowering() = default;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 0562fd8c08ba8..f9d727eaf1e20 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -749,7 +749,8 @@ ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
}
/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
+ const TargetSubtargetInfo &STI)
: TM(tm),
RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
TM.Options.FloatABIType, TM.Options.EABIVersion,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8f41f230b5521..2fc8b0c9a22cd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -387,7 +387,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne.
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index db890df7c50f9..19b3ae5e695c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -60,8 +60,9 @@ unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
- const AMDGPUSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI)
+ : TargetLowering(TM, STI), Subtarget(&AMDGPUSTI) {
// Always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = ~0U;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 473975133f5b3..9c0eff99981cd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -180,7 +180,8 @@ class AMDGPUTargetLowering : public TargetLowering {
const SmallVectorImpl<ISD::InputArg> &Ins) const;
public:
- AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+ AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI);
bool mayIgnoreSignedZero(SDValue Op) const;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index c799c7f63e105..950a9d8649c93 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -30,7 +30,8 @@ using namespace llvm;
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
const R600Subtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
+ Gen(STI.getGeneration()) {
addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e37d739fc25df..1e0f0e5173690 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -87,7 +87,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd8d7a0bee5e3..2ad8f877ff11b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -508,7 +508,7 @@ const ARMBaseTargetMachine &ARMTargetLowering::getTM() const {
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
const ARMSubtarget &STI)
- : TargetLowering(TM_), Subtarget(&STI),
+ : TargetLowering(TM_, STI), Subtarget(&STI),
RegInfo(Subtarget->getRegisterInfo()),
Itins(Subtarget->getInstrItineraryData()) {
const auto &TM = static_cast<const ARMBaseTargetMachine &>(TM_);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 545bc3af05383..054ff989d54b8 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -34,7 +34,7 @@ namespace llvm {
AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index ecefd2379356a..a8d1faa85116b 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -58,7 +58,7 @@ static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg,
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index f0c5f523a003c..fae9cbf9832fe 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -206,7 +206,7 @@ DirectXTargetMachine::getTargetTransformInfo(const Function &F) const {
DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM,
const DirectXSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
addRegisterClass(MVT::i32, &dxil::DXILClassRegClass);
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 894a07e6b68c2..5f953bf53bc7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1504,8 +1504,8 @@ HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &ST)
- : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
- Subtarget(ST) {
+ : TargetLowering(TM, ST),
+ HTM(static_cast<const HexagonTargetMachine &>(TM)), Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();
setPrefLoopAlignment(Align(16));
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index f412f66d9d192..631a8de035ac2 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -70,7 +70,7 @@ static cl::opt<int> LanaiLowerConstantMulThreshold(
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
const LanaiSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cf4ffc82f6009..83d841dba33e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -76,7 +76,7 @@ static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT GRLenVT = Subtarget.getGRLenVT();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5653099431b18..89f38c847b1eb 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -42,7 +42,7 @@ static cl::opt<bool>MSP430NoLegalImmediate(
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 2fd73275721b1..b52aa3ce67950 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -295,7 +295,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
+ : TargetLowering(TM, STI), Subtarget(STI), ABI(TM.getABI()) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8fc3a68de6c79..a77eb0240e677 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -514,7 +514,7 @@ VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
- : TargetLowering(TM), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
+ : TargetLowering(TM, STI), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 220010c4d3d34..9ead9e58f8931 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -174,7 +174,7 @@ extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
const PPCSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Initialize map that relates the PPC addressing modes to the computed flags
// of a load/store instruction. The map is used to determine the optimal
// addressing mode when selecting load and stores.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..3d6d4f6654d17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -95,7 +95,7 @@ static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e742a9811984b..8547ccfa7eaaa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -24,6 +24,10 @@
using namespace llvm;
+SPIRVTargetLowering::SPIRVTargetLowering(const TargetMachine &TM,
+ const SPIRVSubtarget &ST)
+ : TargetLowering(TM, ST), STI(ST) {}
+
// Returns true of the types logically match, as defined in
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 9025e6eb0842e..3d31a116bad4a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -29,8 +29,7 @@ class SPIRVTargetLowering : public TargetLowering {
public:
explicit SPIRVTargetLowering(const TargetMachine &TM,
- const SPIRVSubtarget &ST)
- : TargetLowering(TM), STI(ST) {}
+ const SPIRVSubtarget &ST);
// Stop IRTranslator breaking up FMA instrs to preserve types information.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index ae3c32687c207..dc1196127e3d4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1573,7 +1573,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
// Instructions which use registers as conditionals examine all the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dfd76f9b0427f..06501b745b3f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -92,7 +92,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
auto *Regs = STI.getSpecialRegisters();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e1735424a776b..a64193236f2ad 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -886,7 +886,7 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
// matters much whether it's ZeroOrOneBooleanContent, or
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index ad70d1b7e0a1e..abd8b2e095ae1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
// Set the load count for memcmp expand optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1251a3ca8dbaa..35e1649325932 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,7 @@ static cl::opt<bool> MulConstantOptimization(
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 0a96ab236c6ad..7c49e5b620bdf 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -42,7 +42,7 @@ using namespace llvm;
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM, Subtarget), TM(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 71c98621c81ee..a9cf67128cdef 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -54,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTarge...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-arm Author: Matt Arsenault (arsenm) ChangesCurrently LibcallLoweringInfo is defined inside of TargetLowering, Patch is 25.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168620.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c932c523e423..7df5d8a09f0f6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -355,7 +355,8 @@ class LLVM_ABI TargetLoweringBase {
llvm_unreachable("Invalid content kind");
}
- explicit TargetLoweringBase(const TargetMachine &TM);
+ explicit TargetLoweringBase(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase();
@@ -3977,7 +3978,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
+ explicit TargetLowering(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
~TargetLowering() override;
bool isPositionIndependent() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb64f4ee70280..a2c6a22043001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -41,8 +41,9 @@ using namespace llvm;
using namespace llvm::SDPatternMatch;
/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
- : TargetLoweringBase(tm) {}
+TargetLowering::TargetLowering(const TargetMachine &tm,
+ const TargetSubtargetInfo &sti)
+ : TargetLoweringBase(tm, sti) {}
// Define the virtual destructor out-of-line for build efficiency.
TargetLowering::~TargetLowering() = default;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 0562fd8c08ba8..f9d727eaf1e20 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -749,7 +749,8 @@ ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
}
/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
+ const TargetSubtargetInfo &STI)
: TM(tm),
RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
TM.Options.FloatABIType, TM.Options.EABIVersion,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8f41f230b5521..2fc8b0c9a22cd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -387,7 +387,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne.
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index db890df7c50f9..19b3ae5e695c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -60,8 +60,9 @@ unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
- const AMDGPUSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI)
+ : TargetLowering(TM, STI), Subtarget(&AMDGPUSTI) {
// Always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = ~0U;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 473975133f5b3..9c0eff99981cd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -180,7 +180,8 @@ class AMDGPUTargetLowering : public TargetLowering {
const SmallVectorImpl<ISD::InputArg> &Ins) const;
public:
- AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+ AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI);
bool mayIgnoreSignedZero(SDValue Op) const;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index c799c7f63e105..950a9d8649c93 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -30,7 +30,8 @@ using namespace llvm;
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
const R600Subtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
+ Gen(STI.getGeneration()) {
addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e37d739fc25df..1e0f0e5173690 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -87,7 +87,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd8d7a0bee5e3..2ad8f877ff11b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -508,7 +508,7 @@ const ARMBaseTargetMachine &ARMTargetLowering::getTM() const {
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
const ARMSubtarget &STI)
- : TargetLowering(TM_), Subtarget(&STI),
+ : TargetLowering(TM_, STI), Subtarget(&STI),
RegInfo(Subtarget->getRegisterInfo()),
Itins(Subtarget->getInstrItineraryData()) {
const auto &TM = static_cast<const ARMBaseTargetMachine &>(TM_);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 545bc3af05383..054ff989d54b8 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -34,7 +34,7 @@ namespace llvm {
AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index ecefd2379356a..a8d1faa85116b 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -58,7 +58,7 @@ static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg,
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index f0c5f523a003c..fae9cbf9832fe 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -206,7 +206,7 @@ DirectXTargetMachine::getTargetTransformInfo(const Function &F) const {
DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM,
const DirectXSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
addRegisterClass(MVT::i32, &dxil::DXILClassRegClass);
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 894a07e6b68c2..5f953bf53bc7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1504,8 +1504,8 @@ HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &ST)
- : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
- Subtarget(ST) {
+ : TargetLowering(TM, ST),
+ HTM(static_cast<const HexagonTargetMachine &>(TM)), Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();
setPrefLoopAlignment(Align(16));
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index f412f66d9d192..631a8de035ac2 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -70,7 +70,7 @@ static cl::opt<int> LanaiLowerConstantMulThreshold(
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
const LanaiSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cf4ffc82f6009..83d841dba33e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -76,7 +76,7 @@ static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT GRLenVT = Subtarget.getGRLenVT();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5653099431b18..89f38c847b1eb 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -42,7 +42,7 @@ static cl::opt<bool>MSP430NoLegalImmediate(
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 2fd73275721b1..b52aa3ce67950 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -295,7 +295,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
+ : TargetLowering(TM, STI), Subtarget(STI), ABI(TM.getABI()) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8fc3a68de6c79..a77eb0240e677 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -514,7 +514,7 @@ VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
- : TargetLowering(TM), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
+ : TargetLowering(TM, STI), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 220010c4d3d34..9ead9e58f8931 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -174,7 +174,7 @@ extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
const PPCSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Initialize map that relates the PPC addressing modes to the computed flags
// of a load/store instruction. The map is used to determine the optimal
// addressing mode when selecting load and stores.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..3d6d4f6654d17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -95,7 +95,7 @@ static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e742a9811984b..8547ccfa7eaaa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -24,6 +24,10 @@
using namespace llvm;
+SPIRVTargetLowering::SPIRVTargetLowering(const TargetMachine &TM,
+ const SPIRVSubtarget &ST)
+ : TargetLowering(TM, ST), STI(ST) {}
+
// Returns true of the types logically match, as defined in
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 9025e6eb0842e..3d31a116bad4a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -29,8 +29,7 @@ class SPIRVTargetLowering : public TargetLowering {
public:
explicit SPIRVTargetLowering(const TargetMachine &TM,
- const SPIRVSubtarget &ST)
- : TargetLowering(TM), STI(ST) {}
+ const SPIRVSubtarget &ST);
// Stop IRTranslator breaking up FMA instrs to preserve types information.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index ae3c32687c207..dc1196127e3d4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1573,7 +1573,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
// Instructions which use registers as conditionals examine all the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dfd76f9b0427f..06501b745b3f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -92,7 +92,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
auto *Regs = STI.getSpecialRegisters();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e1735424a776b..a64193236f2ad 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -886,7 +886,7 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
// matters much whether it's ZeroOrOneBooleanContent, or
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index ad70d1b7e0a1e..abd8b2e095ae1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
// Set the load count for memcmp expand optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1251a3ca8dbaa..35e1649325932 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,7 @@ static cl::opt<bool> MulConstantOptimization(
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 0a96ab236c6ad..7c49e5b620bdf 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -42,7 +42,7 @@ using namespace llvm;
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM, Subtarget), TM(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 71c98621c81ee..a9cf67128cdef 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -54,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTarge...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-directx Author: Matt Arsenault (arsenm) ChangesCurrently LibcallLoweringInfo is defined inside of TargetLowering, Patch is 25.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168620.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c932c523e423..7df5d8a09f0f6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -355,7 +355,8 @@ class LLVM_ABI TargetLoweringBase {
llvm_unreachable("Invalid content kind");
}
- explicit TargetLoweringBase(const TargetMachine &TM);
+ explicit TargetLoweringBase(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase();
@@ -3977,7 +3978,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
+ explicit TargetLowering(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
~TargetLowering() override;
bool isPositionIndependent() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb64f4ee70280..a2c6a22043001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -41,8 +41,9 @@ using namespace llvm;
using namespace llvm::SDPatternMatch;
/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
- : TargetLoweringBase(tm) {}
+TargetLowering::TargetLowering(const TargetMachine &tm,
+ const TargetSubtargetInfo &sti)
+ : TargetLoweringBase(tm, sti) {}
// Define the virtual destructor out-of-line for build efficiency.
TargetLowering::~TargetLowering() = default;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 0562fd8c08ba8..f9d727eaf1e20 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -749,7 +749,8 @@ ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
}
/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
+ const TargetSubtargetInfo &STI)
: TM(tm),
RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
TM.Options.FloatABIType, TM.Options.EABIVersion,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8f41f230b5521..2fc8b0c9a22cd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -387,7 +387,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne.
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index db890df7c50f9..19b3ae5e695c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -60,8 +60,9 @@ unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
- const AMDGPUSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI)
+ : TargetLowering(TM, STI), Subtarget(&AMDGPUSTI) {
// Always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = ~0U;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 473975133f5b3..9c0eff99981cd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -180,7 +180,8 @@ class AMDGPUTargetLowering : public TargetLowering {
const SmallVectorImpl<ISD::InputArg> &Ins) const;
public:
- AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+ AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI);
bool mayIgnoreSignedZero(SDValue Op) const;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index c799c7f63e105..950a9d8649c93 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -30,7 +30,8 @@ using namespace llvm;
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
const R600Subtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
+ Gen(STI.getGeneration()) {
addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e37d739fc25df..1e0f0e5173690 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -87,7 +87,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd8d7a0bee5e3..2ad8f877ff11b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -508,7 +508,7 @@ const ARMBaseTargetMachine &ARMTargetLowering::getTM() const {
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
const ARMSubtarget &STI)
- : TargetLowering(TM_), Subtarget(&STI),
+ : TargetLowering(TM_, STI), Subtarget(&STI),
RegInfo(Subtarget->getRegisterInfo()),
Itins(Subtarget->getInstrItineraryData()) {
const auto &TM = static_cast<const ARMBaseTargetMachine &>(TM_);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 545bc3af05383..054ff989d54b8 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -34,7 +34,7 @@ namespace llvm {
AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index ecefd2379356a..a8d1faa85116b 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -58,7 +58,7 @@ static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg,
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index f0c5f523a003c..fae9cbf9832fe 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -206,7 +206,7 @@ DirectXTargetMachine::getTargetTransformInfo(const Function &F) const {
DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM,
const DirectXSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
addRegisterClass(MVT::i32, &dxil::DXILClassRegClass);
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 894a07e6b68c2..5f953bf53bc7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1504,8 +1504,8 @@ HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &ST)
- : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
- Subtarget(ST) {
+ : TargetLowering(TM, ST),
+ HTM(static_cast<const HexagonTargetMachine &>(TM)), Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();
setPrefLoopAlignment(Align(16));
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index f412f66d9d192..631a8de035ac2 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -70,7 +70,7 @@ static cl::opt<int> LanaiLowerConstantMulThreshold(
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
const LanaiSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cf4ffc82f6009..83d841dba33e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -76,7 +76,7 @@ static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT GRLenVT = Subtarget.getGRLenVT();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5653099431b18..89f38c847b1eb 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -42,7 +42,7 @@ static cl::opt<bool>MSP430NoLegalImmediate(
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 2fd73275721b1..b52aa3ce67950 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -295,7 +295,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
+ : TargetLowering(TM, STI), Subtarget(STI), ABI(TM.getABI()) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8fc3a68de6c79..a77eb0240e677 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -514,7 +514,7 @@ VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
- : TargetLowering(TM), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
+ : TargetLowering(TM, STI), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 220010c4d3d34..9ead9e58f8931 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -174,7 +174,7 @@ extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
const PPCSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Initialize map that relates the PPC addressing modes to the computed flags
// of a load/store instruction. The map is used to determine the optimal
// addressing mode when selecting load and stores.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..3d6d4f6654d17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -95,7 +95,7 @@ static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e742a9811984b..8547ccfa7eaaa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -24,6 +24,10 @@
using namespace llvm;
+SPIRVTargetLowering::SPIRVTargetLowering(const TargetMachine &TM,
+ const SPIRVSubtarget &ST)
+ : TargetLowering(TM, ST), STI(ST) {}
+
// Returns true of the types logically match, as defined in
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 9025e6eb0842e..3d31a116bad4a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -29,8 +29,7 @@ class SPIRVTargetLowering : public TargetLowering {
public:
explicit SPIRVTargetLowering(const TargetMachine &TM,
- const SPIRVSubtarget &ST)
- : TargetLowering(TM), STI(ST) {}
+ const SPIRVSubtarget &ST);
// Stop IRTranslator breaking up FMA instrs to preserve types information.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index ae3c32687c207..dc1196127e3d4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1573,7 +1573,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
// Instructions which use registers as conditionals examine all the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dfd76f9b0427f..06501b745b3f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -92,7 +92,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
auto *Regs = STI.getSpecialRegisters();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e1735424a776b..a64193236f2ad 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -886,7 +886,7 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
// matters much whether it's ZeroOrOneBooleanContent, or
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index ad70d1b7e0a1e..abd8b2e095ae1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
// Set the load count for memcmp expand optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1251a3ca8dbaa..35e1649325932 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,7 @@ static cl::opt<bool> MulConstantOptimization(
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 0a96ab236c6ad..7c49e5b620bdf 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -42,7 +42,7 @@ using namespace llvm;
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM, Subtarget), TM(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 71c98621c81ee..a9cf67128cdef 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -54,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTarge...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-mips Author: Matt Arsenault (arsenm) ChangesCurrently LibcallLoweringInfo is defined inside of TargetLowering, Patch is 25.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168620.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c932c523e423..7df5d8a09f0f6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -355,7 +355,8 @@ class LLVM_ABI TargetLoweringBase {
llvm_unreachable("Invalid content kind");
}
- explicit TargetLoweringBase(const TargetMachine &TM);
+ explicit TargetLoweringBase(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase();
@@ -3977,7 +3978,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
+ explicit TargetLowering(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
~TargetLowering() override;
bool isPositionIndependent() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb64f4ee70280..a2c6a22043001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -41,8 +41,9 @@ using namespace llvm;
using namespace llvm::SDPatternMatch;
/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
- : TargetLoweringBase(tm) {}
+TargetLowering::TargetLowering(const TargetMachine &tm,
+ const TargetSubtargetInfo &sti)
+ : TargetLoweringBase(tm, sti) {}
// Define the virtual destructor out-of-line for build efficiency.
TargetLowering::~TargetLowering() = default;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 0562fd8c08ba8..f9d727eaf1e20 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -749,7 +749,8 @@ ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
}
/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
+ const TargetSubtargetInfo &STI)
: TM(tm),
RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
TM.Options.FloatABIType, TM.Options.EABIVersion,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8f41f230b5521..2fc8b0c9a22cd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -387,7 +387,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne.
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index db890df7c50f9..19b3ae5e695c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -60,8 +60,9 @@ unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
- const AMDGPUSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI)
+ : TargetLowering(TM, STI), Subtarget(&AMDGPUSTI) {
// Always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = ~0U;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 473975133f5b3..9c0eff99981cd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -180,7 +180,8 @@ class AMDGPUTargetLowering : public TargetLowering {
const SmallVectorImpl<ISD::InputArg> &Ins) const;
public:
- AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+ AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI);
bool mayIgnoreSignedZero(SDValue Op) const;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index c799c7f63e105..950a9d8649c93 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -30,7 +30,8 @@ using namespace llvm;
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
const R600Subtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
+ Gen(STI.getGeneration()) {
addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e37d739fc25df..1e0f0e5173690 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -87,7 +87,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd8d7a0bee5e3..2ad8f877ff11b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -508,7 +508,7 @@ const ARMBaseTargetMachine &ARMTargetLowering::getTM() const {
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
const ARMSubtarget &STI)
- : TargetLowering(TM_), Subtarget(&STI),
+ : TargetLowering(TM_, STI), Subtarget(&STI),
RegInfo(Subtarget->getRegisterInfo()),
Itins(Subtarget->getInstrItineraryData()) {
const auto &TM = static_cast<const ARMBaseTargetMachine &>(TM_);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 545bc3af05383..054ff989d54b8 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -34,7 +34,7 @@ namespace llvm {
AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index ecefd2379356a..a8d1faa85116b 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -58,7 +58,7 @@ static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg,
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index f0c5f523a003c..fae9cbf9832fe 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -206,7 +206,7 @@ DirectXTargetMachine::getTargetTransformInfo(const Function &F) const {
DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM,
const DirectXSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
addRegisterClass(MVT::i32, &dxil::DXILClassRegClass);
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 894a07e6b68c2..5f953bf53bc7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1504,8 +1504,8 @@ HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &ST)
- : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
- Subtarget(ST) {
+ : TargetLowering(TM, ST),
+ HTM(static_cast<const HexagonTargetMachine &>(TM)), Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();
setPrefLoopAlignment(Align(16));
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index f412f66d9d192..631a8de035ac2 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -70,7 +70,7 @@ static cl::opt<int> LanaiLowerConstantMulThreshold(
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
const LanaiSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cf4ffc82f6009..83d841dba33e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -76,7 +76,7 @@ static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT GRLenVT = Subtarget.getGRLenVT();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5653099431b18..89f38c847b1eb 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -42,7 +42,7 @@ static cl::opt<bool>MSP430NoLegalImmediate(
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 2fd73275721b1..b52aa3ce67950 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -295,7 +295,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
+ : TargetLowering(TM, STI), Subtarget(STI), ABI(TM.getABI()) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8fc3a68de6c79..a77eb0240e677 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -514,7 +514,7 @@ VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
- : TargetLowering(TM), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
+ : TargetLowering(TM, STI), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 220010c4d3d34..9ead9e58f8931 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -174,7 +174,7 @@ extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
const PPCSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Initialize map that relates the PPC addressing modes to the computed flags
// of a load/store instruction. The map is used to determine the optimal
// addressing mode when selecting load and stores.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..3d6d4f6654d17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -95,7 +95,7 @@ static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e742a9811984b..8547ccfa7eaaa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -24,6 +24,10 @@
using namespace llvm;
+SPIRVTargetLowering::SPIRVTargetLowering(const TargetMachine &TM,
+ const SPIRVSubtarget &ST)
+ : TargetLowering(TM, ST), STI(ST) {}
+
// Returns true of the types logically match, as defined in
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 9025e6eb0842e..3d31a116bad4a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -29,8 +29,7 @@ class SPIRVTargetLowering : public TargetLowering {
public:
explicit SPIRVTargetLowering(const TargetMachine &TM,
- const SPIRVSubtarget &ST)
- : TargetLowering(TM), STI(ST) {}
+ const SPIRVSubtarget &ST);
// Stop IRTranslator breaking up FMA instrs to preserve types information.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index ae3c32687c207..dc1196127e3d4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1573,7 +1573,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
// Instructions which use registers as conditionals examine all the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dfd76f9b0427f..06501b745b3f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -92,7 +92,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
auto *Regs = STI.getSpecialRegisters();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e1735424a776b..a64193236f2ad 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -886,7 +886,7 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
// matters much whether it's ZeroOrOneBooleanContent, or
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index ad70d1b7e0a1e..abd8b2e095ae1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
// Set the load count for memcmp expand optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1251a3ca8dbaa..35e1649325932 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,7 @@ static cl::opt<bool> MulConstantOptimization(
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 0a96ab236c6ad..7c49e5b620bdf 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -42,7 +42,7 @@ using namespace llvm;
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM, Subtarget), TM(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 71c98621c81ee..a9cf67128cdef 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -54,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTarge...
[truncated]
|
Member
|
@llvm/pr-subscribers-backend-powerpc Author: Matt Arsenault (arsenm) ChangesCurrently LibcallLoweringInfo is defined inside of TargetLowering, Patch is 25.57 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168620.diff 31 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c932c523e423..7df5d8a09f0f6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -355,7 +355,8 @@ class LLVM_ABI TargetLoweringBase {
llvm_unreachable("Invalid content kind");
}
- explicit TargetLoweringBase(const TargetMachine &TM);
+ explicit TargetLoweringBase(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase();
@@ -3977,7 +3978,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;
- explicit TargetLowering(const TargetMachine &TM);
+ explicit TargetLowering(const TargetMachine &TM,
+ const TargetSubtargetInfo &STI);
~TargetLowering() override;
bool isPositionIndependent() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb64f4ee70280..a2c6a22043001 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -41,8 +41,9 @@ using namespace llvm;
using namespace llvm::SDPatternMatch;
/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
- : TargetLoweringBase(tm) {}
+TargetLowering::TargetLowering(const TargetMachine &tm,
+ const TargetSubtargetInfo &sti)
+ : TargetLoweringBase(tm, sti) {}
// Define the virtual destructor out-of-line for build efficiency.
TargetLowering::~TargetLowering() = default;
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 0562fd8c08ba8..f9d727eaf1e20 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -749,7 +749,8 @@ ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
}
/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm)
+TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
+ const TargetSubtargetInfo &STI)
: TM(tm),
RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
TM.Options.FloatABIType, TM.Options.EABIVersion,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8f41f230b5521..2fc8b0c9a22cd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -387,7 +387,7 @@ extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) {
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne.
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index db890df7c50f9..19b3ae5e695c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -60,8 +60,9 @@ unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
- const AMDGPUSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI)
+ : TargetLowering(TM, STI), Subtarget(&AMDGPUSTI) {
// Always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather then generating calls to memset, mempcy or memmove.
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = ~0U;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 473975133f5b3..9c0eff99981cd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -180,7 +180,8 @@ class AMDGPUTargetLowering : public TargetLowering {
const SmallVectorImpl<ISD::InputArg> &Ins) const;
public:
- AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+ AMDGPUTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI,
+ const AMDGPUSubtarget &AMDGPUSTI);
bool mayIgnoreSignedZero(SDValue Op) const;
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index c799c7f63e105..950a9d8649c93 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -30,7 +30,8 @@ using namespace llvm;
R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
const R600Subtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
+ Gen(STI.getGeneration()) {
addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e37d739fc25df..1e0f0e5173690 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -87,7 +87,7 @@ static unsigned findFirstFreeSGPR(CCState &CCInfo) {
SITargetLowering::SITargetLowering(const TargetMachine &TM,
const GCNSubtarget &STI)
- : AMDGPUTargetLowering(TM, STI), Subtarget(&STI) {
+ : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd8d7a0bee5e3..2ad8f877ff11b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -508,7 +508,7 @@ const ARMBaseTargetMachine &ARMTargetLowering::getTM() const {
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
const ARMSubtarget &STI)
- : TargetLowering(TM_), Subtarget(&STI),
+ : TargetLowering(TM_, STI), Subtarget(&STI),
RegInfo(Subtarget->getRegisterInfo()),
Itins(Subtarget->getInstrItineraryData()) {
const auto &TM = static_cast<const ARMBaseTargetMachine &>(TM_);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 545bc3af05383..054ff989d54b8 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -34,7 +34,7 @@ namespace llvm {
AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
const AVRSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index ecefd2379356a..a8d1faa85116b 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -58,7 +58,7 @@ static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg,
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
const BPFSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index f0c5f523a003c..fae9cbf9832fe 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -206,7 +206,7 @@ DirectXTargetMachine::getTargetTransformInfo(const Function &F) const {
DirectXTargetLowering::DirectXTargetLowering(const DirectXTargetMachine &TM,
const DirectXSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
addRegisterClass(MVT::i32, &dxil::DXILClassRegClass);
computeRegisterProperties(STI.getRegisterInfo());
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 894a07e6b68c2..5f953bf53bc7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1504,8 +1504,8 @@ HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
const HexagonSubtarget &ST)
- : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
- Subtarget(ST) {
+ : TargetLowering(TM, ST),
+ HTM(static_cast<const HexagonTargetMachine &>(TM)), Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();
setPrefLoopAlignment(Align(16));
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index f412f66d9d192..631a8de035ac2 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -70,7 +70,7 @@ static cl::opt<int> LanaiLowerConstantMulThreshold(
LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
const LanaiSubtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index cf4ffc82f6009..83d841dba33e3 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -76,7 +76,7 @@ static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT GRLenVT = Subtarget.getGRLenVT();
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 5653099431b18..89f38c847b1eb 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -42,7 +42,7 @@ static cl::opt<bool>MSP430NoLegalImmediate(
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
const MSP430Subtarget &STI)
- : TargetLowering(TM) {
+ : TargetLowering(TM, STI) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 2fd73275721b1..b52aa3ce67950 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -295,7 +295,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
+ : TargetLowering(TM, STI), Subtarget(STI), ABI(TM.getABI()) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 8fc3a68de6c79..a77eb0240e677 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -514,7 +514,7 @@ VectorizePTXValueVTs(const SmallVectorImpl<EVT> &ValueVTs,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
- : TargetLowering(TM), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
+ : TargetLowering(TM, STI), nvTM(&TM), STI(STI), GlobalUniqueCallSite(0) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset, mempcy or memmove.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 220010c4d3d34..9ead9e58f8931 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -174,7 +174,7 @@ extern cl::opt<bool> ANDIGlueBug;
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
const PPCSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
// Initialize map that relates the PPC addressing modes to the computed flags
// of a load/store instruction. The map is used to determine the optimal
// addressing mode when selecting load and stores.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2d6bb06d689c3..3d6d4f6654d17 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -95,7 +95,7 @@ static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e742a9811984b..8547ccfa7eaaa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -24,6 +24,10 @@
using namespace llvm;
+SPIRVTargetLowering::SPIRVTargetLowering(const TargetMachine &TM,
+ const SPIRVSubtarget &ST)
+ : TargetLowering(TM, ST), STI(ST) {}
+
// Returns true of the types logically match, as defined in
// https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpCopyLogical.
static bool typesLogicallyMatch(const SPIRVType *Ty1, const SPIRVType *Ty2,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 9025e6eb0842e..3d31a116bad4a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -29,8 +29,7 @@ class SPIRVTargetLowering : public TargetLowering {
public:
explicit SPIRVTargetLowering(const TargetMachine &TM,
- const SPIRVSubtarget &ST)
- : TargetLowering(TM), STI(ST) {}
+ const SPIRVSubtarget &ST);
// Stop IRTranslator breaking up FMA instrs to preserve types information.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index ae3c32687c207..dc1196127e3d4 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1573,7 +1573,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
// Instructions which use registers as conditionals examine all the
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dfd76f9b0427f..06501b745b3f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -92,7 +92,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
auto *Regs = STI.getSpecialRegisters();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e1735424a776b..a64193236f2ad 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -886,7 +886,7 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
VETargetLowering::VETargetLowering(const TargetMachine &TM,
const VESubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
// matters much whether it's ZeroOrOneBooleanContent, or
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index ad70d1b7e0a1e..abd8b2e095ae1 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -43,7 +43,7 @@ using namespace llvm;
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
- : TargetLowering(TM), Subtarget(&STI) {
+ : TargetLowering(TM, STI), Subtarget(&STI) {
auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
// Set the load count for memcmp expand optimization
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1251a3ca8dbaa..35e1649325932 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,7 @@ static cl::opt<bool> MulConstantOptimization(
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 0a96ab236c6ad..7c49e5b620bdf 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -42,7 +42,7 @@ using namespace llvm;
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
const XCoreSubtarget &Subtarget)
- : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
+ : TargetLowering(TM, Subtarget), TM(TM), Subtarget(Subtarget) {
// Set up the register classes.
addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 71c98621c81ee..a9cf67128cdef 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -54,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTarge...
[truncated]
|
Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
arsenm
deleted the
users/arsenm/codegen/add-subtarget-targetloweringbase-constructor
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RKSimon
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to RKSimon/llvm-project
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Nov 20, 2025
Fixes experimental M68k target to match llvm#168620
llvm-sync bot
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to arm/arm-toolchain
that referenced
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Nov 20, 2025
…ructor for ARC, CSKY and M68K (#168811) Those were missing in llvm/llvm-project#168620.
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Currently LibcallLoweringInfo is defined inside of TargetLowering,
which is owned by the subtarget. Pass in the subtarget so we can
construct LibcallLoweringInfo with the subtarget. This is a temporary
step that should be revertable in the future, after LibcallLoweringInfo
is moved out of TargetLowering.