[llvm] Use llvm::size (NFC)

llvm/include/llvm/Bitcode/BitcodeConvenience.h

@@ -265,7 +265,7 @@ template <typename ElementTy> class BCRecordCoding<BCArray<ElementTy>> {
     for (auto &element : array)
       ElementTy::assertValid(element);
 #endif
-    buffer.reserve(buffer.size() + std::distance(array.begin(), array.end()));
+    buffer.reserve(buffer.size() + llvm::size(array));
     llvm::append_range(buffer, array);
     Stream.EmitRecordWithAbbrev(code, buffer);
   }

llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/PrintInstructionCount.h

@@ -13,7 +13,7 @@ class PrintInstructionCount final : public RegionPass {
 public:
   PrintInstructionCount() : RegionPass("null") {}
   bool runOnRegion(Region &R, const Analyses &A) final {
-    outs() << "InstructionCount: " << std::distance(R.begin(), R.end()) << "\n";
+    outs() << "InstructionCount: " << llvm::size(R) << "\n";
     return false;
   }
 };

llvm/lib/CAS/OnDiskCAS.cpp

@@ -63,7 +63,7 @@ class OnDiskCAS : public BuiltinCAS {
 
   size_t getNumRefs(ObjectHandle Node) const final {
     auto RefsRange = DB->getObjectRefs(convertHandle(Node));
-    return std::distance(RefsRange.begin(), RefsRange.end());
+    return llvm::size(RefsRange);
   }
 
   ObjectRef readRef(ObjectHandle Node, size_t I) const final {

llvm/lib/CAS/OnDiskGraphDB.cpp

@@ -1660,9 +1660,8 @@ Error OnDiskGraphDB::importFullTree(ObjectID PrimaryID,
     if (!Node)
       return;
     auto Refs = UpstreamDB->getObjectRefs(*Node);
-    CursorStack.push_back({*Node,
-                           (size_t)std::distance(Refs.begin(), Refs.end()),
-                           Refs.begin(), Refs.end()});
+    CursorStack.push_back(
+        {*Node, (size_t)llvm::size(Refs), Refs.begin(), Refs.end()});
   };
 
   enqueueNode(PrimaryID, UpstreamNode);
@@ -1722,7 +1721,7 @@ Error OnDiskGraphDB::importSingleNode(ObjectID PrimaryID,
   auto Data = UpstreamDB->getObjectData(UpstreamNode);
   auto UpstreamRefs = UpstreamDB->getObjectRefs(UpstreamNode);
   SmallVector<ObjectID, 64> Refs;
-  Refs.reserve(std::distance(UpstreamRefs.begin(), UpstreamRefs.end()));
+  Refs.reserve(llvm::size(UpstreamRefs));
   for (ObjectID UpstreamRef : UpstreamRefs) {
     auto Ref = getReference(UpstreamDB->getDigest(UpstreamRef));
     if (LLVM_UNLIKELY(!Ref))

llvm/lib/ObjectYAML/MinidumpEmitter.cpp

@@ -84,7 +84,7 @@ class BlobAllocator {
 template <typename T, typename RangeType>
 std::pair<size_t, MutableArrayRef<T>>
 BlobAllocator::allocateNewArray(const iterator_range<RangeType> &Range) {
-  size_t Num = std::distance(Range.begin(), Range.end());
+  size_t Num = llvm::size(Range);
   MutableArrayRef<T> Array(Temporaries.Allocate<T>(Num), Num);
   llvm::uninitialized_copy(Range, Array.begin());
   return {allocateArray(Array), Array};

llvm/lib/Support/BalancedPartitioning.cpp

@@ -114,7 +114,7 @@ void BalancedPartitioning::bisect(const FunctionNodeRange Nodes,
                                   unsigned RecDepth, unsigned RootBucket,
                                   unsigned Offset,
                                   std::optional<BPThreadPool> &TP) const {
-  unsigned NumNodes = std::distance(Nodes.begin(), Nodes.end());
+  unsigned NumNodes = llvm::size(Nodes);
   if (NumNodes <= 1 || RecDepth >= Config.SplitDepth) {
     // We've reach the lowest level of the recursion tree. Fall back to the
     // original order and assign to buckets.
@@ -168,7 +168,7 @@ void BalancedPartitioning::runIterations(const FunctionNodeRange Nodes,
                                          unsigned LeftBucket,
                                          unsigned RightBucket,
                                          std::mt19937 &RNG) const {
-  unsigned NumNodes = std::distance(Nodes.begin(), Nodes.end());
+  unsigned NumNodes = llvm::size(Nodes);
   DenseMap<BPFunctionNode::UtilityNodeT, unsigned> UtilityNodeIndex;
   for (auto &N : Nodes)
     for (auto &UN : N.UtilityNodes)
@@ -303,7 +303,7 @@ bool BalancedPartitioning::moveFunctionNode(BPFunctionNode &N,
 
 void BalancedPartitioning::split(const FunctionNodeRange Nodes,
                                  unsigned StartBucket) const {
-  unsigned NumNodes = std::distance(Nodes.begin(), Nodes.end());
+  unsigned NumNodes = llvm::size(Nodes);
   auto NodesMid = Nodes.begin() + (NumNodes + 1) / 2;
 
   llvm::sort(Nodes, [](auto &L, auto &R) {

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

@@ -1266,9 +1266,7 @@ void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
   // Frame address.  Currently handles register +- offset only.
   assert(MI->isIndirectDebugValue());
   OS << '[';
-  for (unsigned I = 0, E = std::distance(MI->debug_operands().begin(),
-                                         MI->debug_operands().end());
-       I < E; ++I) {
+  for (unsigned I = 0, E = llvm::size(MI->debug_operands()); I < E; ++I) {
     if (I != 0)
       OS << ", ";
     printOperand(MI, I, OS);

llvm/lib/Target/AMDGPU/GCNRegPressure.h

@@ -455,7 +455,7 @@ template <typename Range>
 DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
   std::vector<SlotIndex> Indexes;
-  Indexes.reserve(std::distance(R.begin(), R.end()));
+  Indexes.reserve(llvm::size(R));
   auto &SII = *LIS.getSlotIndexes();
   for (MachineInstr *I : R) {
     auto SI = SII.getInstructionIndex(*I);

llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp

@@ -606,8 +606,7 @@ bool SPIRVTargetLowering::insertLogicalCopyOnResult(
       createVirtualRegister(NewResultType, &GR, MRI, *I.getMF());
   Register NewTypeReg = GR.getSPIRVTypeID(NewResultType);
 
-  assert(std::distance(I.defs().begin(), I.defs().end()) == 1 &&
-         "Expected only one def");
+  assert(llvm::size(I.defs()) == 1 && "Expected only one def");
   MachineOperand &OldResult = *I.defs().begin();
   Register OldResultReg = OldResult.getReg();
   MachineOperand &OldType = *I.uses().begin();

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

@@ -1067,8 +1067,7 @@ static void removeImplicitFallthroughs(MachineFunction &MF,
     if (!isImplicitFallthrough(MBB))
       continue;
 
-    assert(std::distance(MBB.successors().begin(), MBB.successors().end()) ==
-           1);
+    assert(MBB.succ_size() == 1);
     MIB.setInsertPt(MBB, MBB.end());
     MIB.buildBr(**MBB.successors().begin());
   }

llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp

@@ -2914,8 +2914,8 @@ static int CalculateUnswitchCostMultiplier(
     ParentLoopSizeMultiplier =
         std::max<int>(ParentL->getNumBlocks() / UnswitchParentBlocksDiv, 1);
 
-  int SiblingsCount = (ParentL ? ParentL->getSubLoopsVector().size()
-                               : std::distance(LI.begin(), LI.end()));
+  int SiblingsCount =
+      (ParentL ? ParentL->getSubLoopsVector().size() : llvm::size(LI));
   // Count amount of clones that all the candidates might cause during
   // unswitching. Branch/guard/select counts as 1, switch counts as log2 of its
   // cases.

llvm/tools/llvm-xray/xray-extract.cpp

@@ -57,7 +57,7 @@ static void exportAsYAML(const InstrumentationMap &Map, raw_ostream &OS,
   // First we translate the sleds into the YAMLXRaySledEntry objects in a deque.
   std::vector<YAMLXRaySledEntry> YAMLSleds;
   auto Sleds = Map.sleds();
-  YAMLSleds.reserve(std::distance(Sleds.begin(), Sleds.end()));
+  YAMLSleds.reserve(llvm::size(Sleds));
   for (const auto &Sled : Sleds) {
     auto FuncId = Map.getFunctionId(Sled.Function);
     if (!FuncId)

llvm/utils/TableGen/RegisterInfoEmitter.cpp

@@ -703,8 +703,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
   SmallVector<unsigned, 4> RowMap;
   SmallVector<SmallVector<const CodeGenSubRegIndex *, 4>, 4> Rows;
 
-  auto SubRegIndicesSize =
-      std::distance(SubRegIndices.begin(), SubRegIndices.end());
+  auto SubRegIndicesSize = llvm::size(SubRegIndices);
   for (const auto &Idx : SubRegIndices) {
     unsigned Found = ~0u;
     for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
@@ -1133,7 +1132,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
      << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
      << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
-     << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
+     << (llvm::size(SubRegIndices) + 1) << ",\n"
      << TargetName << "RegEncodingTable);\n\n";
 
   EmitRegMapping(OS, Regs, false);
@@ -1527,8 +1526,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
 
   std::string ClassName = Target.getName().str() + "GenRegisterInfo";
 
-  auto SubRegIndicesSize =
-      std::distance(SubRegIndices.begin(), SubRegIndices.end());
+  auto SubRegIndicesSize = llvm::size(SubRegIndices);
 
   if (!SubRegIndices.empty()) {
     emitComposeSubRegIndices(OS, ClassName);