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[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 #168719

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[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 #168719

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5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -6806,6 +6806,11 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return splitTernaryVectorOp(Op, DAG);
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
if (AMDGPU::isGFX11Plus(*Subtarget) && Op.getValueType() == MVT::i16 &&
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@arsenm arsenm Nov 20, 2025

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Don't use AMDGPU::isGFX11Plus, use the method directly on the subtarget. The standalone predicates are a hack for MC.

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@arsenm arsenm Nov 20, 2025

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Also better to not do this with a generation check

Op.getOperand(0).getValueType() == MVT::f32) {
// Make f32->i16 legal so we can select V_CVT_PK_[IU]16_F32.
return Op;
}
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@arsenm arsenm Nov 20, 2025

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Why not sink this into LowerFP_TO_INT?

return LowerFP_TO_INT(Op, DAG);
case ISD::SHL:
case ISD::SRA:
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Expand Up @@ -469,6 +469,14 @@ let SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE],
} // End SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE]
// SchedRW = [WriteSFPU], isReMaterializable = 1

let SubtargetPredicate = HasSALUFloatInsts, AddedComplexity = 9 in {
// Fallback patterns for f32->i16 conversion.
def : GCNPat<(i16 (UniformUnaryFrag<fp_to_sint> f32:$src0)),
(S_CVT_I32_F32 $src0)>;
def : GCNPat<(i16 (UniformUnaryFrag<fp_to_uint> f32:$src0)),
(S_CVT_U32_F32 $src0)>;
}

let hasSideEffects = 1 in {
let has_sdst = 0 in {
let Uses = [M0] in {
Expand Down
22 changes: 22 additions & 0 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -1721,6 +1721,28 @@ let SubtargetPredicate = isGFX11Plus in {
defm V_MINMAX_I32 : VOP3Inst<"v_minmax_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
defm V_CVT_PK_I16_F32 : VOP3Inst<"v_cvt_pk_i16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>;
defm V_CVT_PK_U16_F32 : VOP3Inst<"v_cvt_pk_u16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>;

def : GCNPat<(v2i16 (build_vector (i16 (fp_to_sint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(i16 (fp_to_sint (f32 (VOP3Mods f32:$src1, i32:$src1_modifiers)))))),
(V_CVT_PK_I16_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1)>;
def : GCNPat<(v2i16 (build_vector (i16 (fp_to_uint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(i16 (fp_to_uint (f32 (VOP3Mods f32:$src1, i32:$src1_modifiers)))))),
(V_CVT_PK_U16_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1)>;

// Fallback patterns for f32->i16 conversion. These are only required because
// f32->i16 has to be legal so that we can select V_CVT_PK_[IU]16_F32 above.
let True16Predicate = UseRealTrue16Insts in {
def : GCNPat<(i16 (fp_to_sint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(EXTRACT_SUBREG (V_CVT_I32_F32_e64 $src0_modifiers, $src0), lo16)>;
def : GCNPat<(i16 (fp_to_uint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(EXTRACT_SUBREG (V_CVT_U32_F32_e64 $src0_modifiers, $src0), lo16)>;
}
let True16Predicate = NotUseRealTrue16Insts in {
def : GCNPat<(i16 (fp_to_sint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(V_CVT_I32_F32_e64 $src0_modifiers, $src0)>;
def : GCNPat<(i16 (fp_to_uint (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
(V_CVT_U32_F32_e64 $src0_modifiers, $src0)>;
}
} // End SubtargetPredicate = isGFX11Plus

class VOP3_CVT_SR_FP16_TiedInput_Profile<VOPProfile P> : VOP3_CVT_SCALE_F1632_FP8BF8_TiedInput_Profile<P> {
Expand Down
231 changes: 59 additions & 172 deletions llvm/test/CodeGen/AMDGPU/bf16.ll
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Expand Up @@ -35513,55 +35513,24 @@ define <2 x i16> @v_fptosi_v2bf16_to_v2i16(<2 x bfloat> %x) {
; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11TRUE16-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GFX1250TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
; GFX11-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cvt_pk_i16_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250FAKE16-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100
; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX1250-LABEL: v_fptosi_v2bf16_to_v2i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_pk_i16_f32 v0, v0, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%op = fptosi <2 x bfloat> %x to <2 x i16>
ret <2 x i16> %op
}
Expand Down Expand Up @@ -35655,61 +35624,27 @@ define <3 x i16> @v_fptosi_v3bf16_to_v3i16(<3 x bfloat> %x) {
; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11TRUE16-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
; GFX11-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
; GFX11-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX1250-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cvt_pk_i16_f32 v0, v0, v2
; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%op = fptosi <3 x bfloat> %x to <3 x i16>
ret <3 x i16> %op
}
Expand Down Expand Up @@ -35827,77 +35762,29 @@ define <4 x i16> @v_fptosi_v4bf16_to_v4i16(<4 x bfloat> %x) {
; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11TRUE16-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX11FAKE16: ; %bb.0:
; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
; GFX1250TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
; GFX11-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cvt_pk_i16_f32 v0, v0, v3
; GFX11-NEXT: v_cvt_pk_i16_f32 v1, v1, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250FAKE16-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX1250FAKE16: ; %bb.0:
; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v1 :: v_dual_lshlrev_b32 v3, 16, v0
; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
; GFX1250FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
; GFX1250-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-NEXT: v_cvt_pk_i16_f32 v0, v0, v3
; GFX1250-NEXT: v_cvt_pk_i16_f32 v1, v1, v2
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%op = fptosi <4 x bfloat> %x to <4 x i16>
ret <4 x i16> %op
}
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