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[DAG] Fold mul 0 -> 0 when expanding mul into parts. #168780

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[DAG] Fold mul 0 -> 0 when expanding mul into parts. #168780

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2 changes: 2 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -7615,6 +7615,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
N1.getValueType() == VT && "Binary operator types must match!");
if (VT.getScalarType() == MVT::i1)
return getNode(ISD::AND, DL, VT, N1, N2);
if (N2CV && N2CV->isZero())
return N2;
if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) {
const APInt &MulImm = N1->getConstantOperandAPInt(0);
const APInt &N2CImm = N2C->getAPIntValue();
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AArch64/combine-sdiv.ll
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Expand Up @@ -1674,8 +1674,9 @@ define i32 @combine_i32_sdiv_const100(i32 %x) {
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: smull x8, w0, w8
; CHECK-SD-NEXT: lsr x9, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: add w0, w8, w8, lsr #31
; CHECK-SD-NEXT: add w0, w8, w9
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i32_sdiv_const100:
Expand Down
130 changes: 75 additions & 55 deletions llvm/test/CodeGen/AArch64/rem-by-const.ll
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Expand Up @@ -279,11 +279,12 @@ define i32 @si32_100(i32 %a, i32 %b) {
; CHECK-SD-LABEL: si32_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: mov w9, #100 // =0x64
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: smull x8, w0, w8
; CHECK-SD-NEXT: lsr x9, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
; CHECK-SD-NEXT: add w8, w8, w9
; CHECK-SD-NEXT: mov w9, #100 // =0x64
; CHECK-SD-NEXT: msub w0, w8, w9, w0
; CHECK-SD-NEXT: ret
;
Expand Down Expand Up @@ -723,17 +724,19 @@ entry:
define <2 x i8> @sv2i8_100(<2 x i8> %d, <2 x i8> %e) {
; CHECK-SD-LABEL: sv2i8_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: movi v2.2s, #100
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24
; CHECK-SD-NEXT: movi v3.2s, #100
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: dup v1.2s, w8
; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-SD-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-SD-NEXT: sshr v1.2d, v1.2d, #37
; CHECK-SD-NEXT: xtn v2.2s, v2.2d
; CHECK-SD-NEXT: xtn v1.2s, v1.2d
; CHECK-SD-NEXT: usra v1.2s, v1.2s, #31
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv2i8_100:
Expand Down Expand Up @@ -856,22 +859,25 @@ define <3 x i8> @sv3i8_100(<3 x i8> %d, <3 x i8> %e) {
; CHECK-SD-NEXT: sxtb x10, w1
; CHECK-SD-NEXT: movk w9, #20971, lsl #16
; CHECK-SD-NEXT: sxtb x11, w2
; CHECK-SD-NEXT: sxtb w12, w0
; CHECK-SD-NEXT: mov w12, #100 // =0x64
; CHECK-SD-NEXT: smull x8, w8, w9
; CHECK-SD-NEXT: smull x10, w10, w9
; CHECK-SD-NEXT: smull x9, w11, w9
; CHECK-SD-NEXT: mov w11, #100 // =0x64
; CHECK-SD-NEXT: lsr x11, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: lsr x13, x10, #63
; CHECK-SD-NEXT: asr x10, x10, #37
; CHECK-SD-NEXT: add w8, w8, w11
; CHECK-SD-NEXT: lsr x11, x9, #63
; CHECK-SD-NEXT: asr x9, x9, #37
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
; CHECK-SD-NEXT: add w10, w10, w10, lsr #31
; CHECK-SD-NEXT: add w9, w9, w9, lsr #31
; CHECK-SD-NEXT: msub w0, w8, w11, w12
; CHECK-SD-NEXT: add w10, w10, w13
; CHECK-SD-NEXT: sxtb w13, w0
; CHECK-SD-NEXT: msub w0, w8, w12, w13
; CHECK-SD-NEXT: sxtb w8, w1
; CHECK-SD-NEXT: msub w1, w10, w11, w8
; CHECK-SD-NEXT: add w9, w9, w11
; CHECK-SD-NEXT: msub w1, w10, w12, w8
; CHECK-SD-NEXT: sxtb w8, w2
; CHECK-SD-NEXT: msub w2, w9, w11, w8
; CHECK-SD-NEXT: msub w2, w9, w12, w8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv3i8_100:
Expand Down Expand Up @@ -989,33 +995,37 @@ define <4 x i8> @sv4i8_100(<4 x i8> %d, <4 x i8> %e) {
; CHECK-SD-NEXT: mov w14, #100 // =0x64
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: sshr v1.4h, v0.4h, #8
; CHECK-SD-NEXT: smov x9, v1.h[0]
; CHECK-SD-NEXT: smov x10, v1.h[1]
; CHECK-SD-NEXT: smov x10, v1.h[0]
; CHECK-SD-NEXT: smov x9, v1.h[1]
; CHECK-SD-NEXT: smov x11, v1.h[2]
; CHECK-SD-NEXT: smov w12, v1.h[0]
; CHECK-SD-NEXT: smov x13, v1.h[3]
; CHECK-SD-NEXT: smov w16, v1.h[0]
; CHECK-SD-NEXT: smov w15, v1.h[1]
; CHECK-SD-NEXT: smull x9, w9, w8
; CHECK-SD-NEXT: smull x10, w10, w8
; CHECK-SD-NEXT: smull x9, w9, w8
; CHECK-SD-NEXT: smull x11, w11, w8
; CHECK-SD-NEXT: asr x9, x9, #37
; CHECK-SD-NEXT: smull x8, w13, w8
; CHECK-SD-NEXT: lsr x13, x10, #63
; CHECK-SD-NEXT: asr x10, x10, #37
; CHECK-SD-NEXT: add w9, w9, w9, lsr #31
; CHECK-SD-NEXT: lsr x12, x9, #63
; CHECK-SD-NEXT: asr x9, x9, #37
; CHECK-SD-NEXT: add w10, w10, w13
; CHECK-SD-NEXT: smov x13, v1.h[3]
; CHECK-SD-NEXT: msub w10, w10, w14, w16
; CHECK-SD-NEXT: add w9, w9, w12
; CHECK-SD-NEXT: lsr x12, x11, #63
; CHECK-SD-NEXT: msub w9, w9, w14, w15
; CHECK-SD-NEXT: asr x11, x11, #37
; CHECK-SD-NEXT: add w10, w10, w10, lsr #31
; CHECK-SD-NEXT: fmov s0, w10
; CHECK-SD-NEXT: smull x8, w13, w8
; CHECK-SD-NEXT: smov w10, v1.h[2]
; CHECK-SD-NEXT: mov v0.h[1], w9
; CHECK-SD-NEXT: add w9, w11, w12
; CHECK-SD-NEXT: smov w11, v1.h[3]
; CHECK-SD-NEXT: msub w9, w9, w14, w10
; CHECK-SD-NEXT: lsr x10, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: msub w9, w9, w14, w12
; CHECK-SD-NEXT: msub w10, w10, w14, w15
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
; CHECK-SD-NEXT: fmov s0, w9
; CHECK-SD-NEXT: add w9, w11, w11, lsr #31
; CHECK-SD-NEXT: smov w11, v1.h[2]
; CHECK-SD-NEXT: msub w9, w9, w14, w11
; CHECK-SD-NEXT: mov v0.h[1], w10
; CHECK-SD-NEXT: smov w10, v1.h[3]
; CHECK-SD-NEXT: msub w8, w8, w14, w10
; CHECK-SD-NEXT: add w8, w8, w10
; CHECK-SD-NEXT: mov v0.h[2], w9
; CHECK-SD-NEXT: msub w8, w8, w14, w11
; CHECK-SD-NEXT: mov v0.h[3], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
Expand Down Expand Up @@ -1716,17 +1726,19 @@ entry:
define <2 x i16> @sv2i16_100(<2 x i16> %d, <2 x i16> %e) {
; CHECK-SD-LABEL: sv2i16_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: movi v2.2s, #100
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: movi v3.2s, #100
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: dup v1.2s, w8
; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16
; CHECK-SD-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-SD-NEXT: sshr v1.2d, v1.2d, #37
; CHECK-SD-NEXT: xtn v2.2s, v2.2d
; CHECK-SD-NEXT: xtn v1.2s, v1.2d
; CHECK-SD-NEXT: usra v1.2s, v1.2s, #31
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv2i16_100:
Expand Down Expand Up @@ -1839,23 +1851,26 @@ define <3 x i16> @sv3i16_100(<3 x i16> %d, <3 x i16> %e) {
; CHECK-SD-NEXT: smov x10, v0.h[1]
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: smov x11, v0.h[2]
; CHECK-SD-NEXT: mov w12, #100 // =0x64
; CHECK-SD-NEXT: smov w13, v0.h[1]
; CHECK-SD-NEXT: smov w13, v0.h[0]
; CHECK-SD-NEXT: mov w14, #100 // =0x64
; CHECK-SD-NEXT: smull x9, w9, w8
; CHECK-SD-NEXT: smull x10, w10, w8
; CHECK-SD-NEXT: smull x8, w11, w8
; CHECK-SD-NEXT: smov w11, v0.h[0]
; CHECK-SD-NEXT: lsr x11, x9, #63
; CHECK-SD-NEXT: asr x9, x9, #37
; CHECK-SD-NEXT: lsr x12, x10, #63
; CHECK-SD-NEXT: asr x10, x10, #37
; CHECK-SD-NEXT: add w9, w9, w9, lsr #31
; CHECK-SD-NEXT: add w9, w9, w11
; CHECK-SD-NEXT: smov w11, v0.h[1]
; CHECK-SD-NEXT: msub w9, w9, w14, w13
; CHECK-SD-NEXT: add w10, w10, w12
; CHECK-SD-NEXT: smov w12, v0.h[2]
; CHECK-SD-NEXT: msub w10, w10, w14, w11
; CHECK-SD-NEXT: lsr x11, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: add w10, w10, w10, lsr #31
; CHECK-SD-NEXT: msub w9, w9, w12, w11
; CHECK-SD-NEXT: smov w11, v0.h[2]
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
; CHECK-SD-NEXT: msub w10, w10, w12, w13
; CHECK-SD-NEXT: msub w8, w8, w12, w11
; CHECK-SD-NEXT: fmov s0, w9
; CHECK-SD-NEXT: add w8, w8, w11
; CHECK-SD-NEXT: msub w8, w8, w14, w12
; CHECK-SD-NEXT: mov v0.h[1], w10
; CHECK-SD-NEXT: mov v0.h[2], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
Expand Down Expand Up @@ -2407,14 +2422,16 @@ define <2 x i32> @sv2i32_100(<2 x i32> %d, <2 x i32> %e) {
; CHECK-SD-LABEL: sv2i32_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: movi v2.2s, #100
; CHECK-SD-NEXT: movi v3.2s, #100
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: dup v1.2s, w8
; CHECK-SD-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-SD-NEXT: sshr v1.2d, v1.2d, #37
; CHECK-SD-NEXT: xtn v2.2s, v2.2d
; CHECK-SD-NEXT: xtn v1.2s, v1.2d
; CHECK-SD-NEXT: usra v1.2s, v1.2s, #31
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv2i32_100:
Expand Down Expand Up @@ -2492,19 +2509,22 @@ define <3 x i32> @sv3i32_100(<3 x i32> %d, <3 x i32> %e) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: mov w9, v0.s[2]
; CHECK-SD-NEXT: movi v2.2s, #100
; CHECK-SD-NEXT: movi v3.2s, #100
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: mov w10, #100 // =0x64
; CHECK-SD-NEXT: dup v1.2s, w8
; CHECK-SD-NEXT: smull x8, w9, w8
; CHECK-SD-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-SD-NEXT: lsr x10, x8, #63
; CHECK-SD-NEXT: asr x8, x8, #37
; CHECK-SD-NEXT: add w8, w8, w8, lsr #31
; CHECK-SD-NEXT: add w8, w8, w10
; CHECK-SD-NEXT: mov w10, #100 // =0x64
; CHECK-SD-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-SD-NEXT: sshr v1.2d, v1.2d, #37
; CHECK-SD-NEXT: msub w8, w8, w10, w9
; CHECK-SD-NEXT: xtn v2.2s, v2.2d
; CHECK-SD-NEXT: xtn v1.2s, v1.2d
; CHECK-SD-NEXT: usra v1.2s, v1.2s, #31
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-SD-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-SD-NEXT: mov v0.s[2], w8
; CHECK-SD-NEXT: ret
;
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/AArch64/srem-lkk.ll
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Expand Up @@ -23,11 +23,12 @@ define i32 @fold_srem_positive_even(i32 %x) {
; CHECK-LABEL: fold_srem_positive_even:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #36849 // =0x8ff1
; CHECK-NEXT: mov w9, #1060 // =0x424
; CHECK-NEXT: movk w8, #15827, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #1060 // =0x424
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, 1060
Expand All @@ -39,11 +40,12 @@ define i32 @fold_srem_negative_odd(i32 %x) {
; CHECK-LABEL: fold_srem_negative_odd:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65445 // =0xffa5
; CHECK-NEXT: mov w9, #-723 // =0xfffffd2d
; CHECK-NEXT: movk w8, #42330, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #-723 // =0xfffffd2d
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, -723
Expand All @@ -55,11 +57,12 @@ define i32 @fold_srem_negative_even(i32 %x) {
; CHECK-LABEL: fold_srem_negative_even:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #62439 // =0xf3e7
; CHECK-NEXT: mov w9, #-22981 // =0xffffa63b
; CHECK-NEXT: movk w8, #64805, lsl #16
; CHECK-NEXT: smull x8, w0, w8
; CHECK-NEXT: lsr x9, x8, #63
; CHECK-NEXT: asr x8, x8, #40
; CHECK-NEXT: add w8, w8, w8, lsr #31
; CHECK-NEXT: add w8, w8, w9
; CHECK-NEXT: mov w9, #-22981 // =0xffffa63b
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, -22981
Expand Down
8 changes: 5 additions & 3 deletions llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
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Expand Up @@ -263,14 +263,16 @@ define <2 x i32> @fold_srem_v2i32(<2 x i32> %x) {
; CHECK-LABEL: fold_srem_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #26215 // =0x6667
; CHECK-NEXT: movi v2.2s, #10
; CHECK-NEXT: movi v3.2s, #10
; CHECK-NEXT: movk w8, #26214, lsl #16
; CHECK-NEXT: dup v1.2s, w8
; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
; CHECK-NEXT: ushr v2.2d, v1.2d, #63
; CHECK-NEXT: sshr v1.2d, v1.2d, #34
; CHECK-NEXT: xtn v2.2s, v2.2d
; CHECK-NEXT: xtn v1.2s, v1.2d
; CHECK-NEXT: usra v1.2s, v1.2s, #31
; CHECK-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-NEXT: ret
%1 = srem <2 x i32> %x, <i32 10, i32 10>
ret <2 x i32> %1
Expand Down
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