[RISCV] Add segmented tunes to tt-ascalon-d8

[ppenzin]

Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8 processor definition.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Petr Penzin (ppenzin)

Changes

Add TuneOptimizedNFnSegmentedLoadStore tune flags to tt-ascalon-d8 processor definition.

---

Full diff: https://github.com/llvm/llvm-project/pull/168800.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+7)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e86431f78f1ba..07f6a38c77897 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -633,6 +633,13 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
                                                   FeatureUnalignedVectorMem]),
                                                  [TuneNoDefaultUnroll,
                                                   TuneNLogNVRGather,
+                                                  TuneOptimizedNF2SegmentLoadStore,
+                                                  TuneOptimizedNF3SegmentLoadStore,
+                                                  TuneOptimizedNF4SegmentLoadStore,
+                                                  TuneOptimizedNF5SegmentLoadStore,
+                                                  TuneOptimizedNF6SegmentLoadStore,
+                                                  TuneOptimizedNF7SegmentLoadStore,
+                                                  TuneOptimizedNF8SegmentLoadStore,
                                                   TuneOptimizedZeroStrideLoad,
                                                   TunePostRAScheduler]>;
 

[ppenzin]

Separated from #167066

[github-actions]

🐧 Linux x64 Test Results

• 186406 tests passed
• 4868 tests skipped

[wangpc-pp]

LGTM.

[preames]

LGTM

[topperc]

LGTM