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Merged
merged 1 commit into from
Nov 21, 2025
Merged

AMDGPU: Convert constant-address-space-32bit test to generated checks #168975

merged 1 commit into from
Nov 21, 2025

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@arsenm arsenm commented Nov 21, 2025

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arsenm commented Nov 21, 2025 •
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@arsenm arsenm mentioned this pull request Nov 21, 2025
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llvmbot commented Nov 21, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Patch is 44.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/168975.diff

1 Files Affected:

  • (modified) llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll (+824-144)
diff --git a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
index 52ccfe8ba3bfb..14056257665b4 100644
--- a/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
@@ -1,17 +1,45 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SICIVI,SICI,SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GCN,SICIVI,SICI %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,SICIVI,VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX67,GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GFX67,GFX7 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX89,GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
 
-; GCN-LABEL: {{^}}load_i32:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
-; SICI-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x2
-; GFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
-; GFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
 define amdgpu_vs float @load_i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_i32:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX67-NEXT:    s_load_dword s1, s[2:3], 0x2
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    s_add_i32 s0, s0, s1
+; GFX67-NEXT:    v_mov_b32_e32 v0, s0
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: load_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s3, 0
+; GFX8-NEXT:    s_mov_b32 s2, s1
+; GFX8-NEXT:    s_mov_b32 s1, s3
+; GFX8-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX8-NEXT:    s_load_dword s1, s[2:3], 0x8
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s0, s0, s1
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: load_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s3, 0
+; GFX9-NEXT:    s_mov_b32 s2, s1
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x0
+; GFX9-NEXT:    s_load_dword s5, s[2:3], 0x8
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s4, s4, s5
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds i32, ptr addrspace(6) %p1, i32 2
   %r0 = load i32, ptr addrspace(6) %p0
   %r1 = load i32, ptr addrspace(6) %gep1
@@ -20,20 +48,48 @@ define amdgpu_vs float @load_i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) in
   ret float %r2
 }
 
-; GCN-LABEL: {{^}}load_v2i32:
-; SICIVI-DAG: s_mov_b32 s3, 0
-; SICIVI-DAG: s_mov_b32 s2, s1
-; SICIVI-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
-; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
-; GFX9-DAG: s_mov_b32 s2, s1
-; GFX9-DAG: s_mov_b32 s3, 0
-; GFX9-DAG: s_mov_b32 s1, s3
-; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
 define amdgpu_vs <2 x float> @load_v2i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v2i32:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x4
+; GFX67-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    s_add_i32 s0, s0, s2
+; GFX67-NEXT:    s_add_i32 s1, s1, s3
+; GFX67-NEXT:    v_mov_b32_e32 v0, s0
+; GFX67-NEXT:    v_mov_b32_e32 v1, s1
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: load_v2i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s3, 0
+; GFX8-NEXT:    s_mov_b32 s2, s1
+; GFX8-NEXT:    s_mov_b32 s1, s3
+; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x10
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s0, s0, s2
+; GFX8-NEXT:    s_add_i32 s1, s1, s3
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: load_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, s1
+; GFX9-NEXT:    s_mov_b32 s3, 0
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x10
+; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s0, s6, s4
+; GFX9-NEXT:    s_add_i32 s1, s7, s5
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds <2 x i32>, ptr addrspace(6) %p1, i32 2
   %r0 = load <2 x i32>, ptr addrspace(6) %p0
   %r1 = load <2 x i32>, ptr addrspace(6) %gep1
@@ -42,17 +98,60 @@ define amdgpu_vs <2 x float> @load_v2i32(ptr addrspace(6) inreg %p0, ptr addrspa
   ret <2 x float> %r2
 }
 
-; GCN-LABEL: {{^}}load_v4i32:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
-; VI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
-; GFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
 define amdgpu_vs <4 x float> @load_v4i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v4i32:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x8
+; GFX67-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    s_add_i32 s0, s0, s4
+; GFX67-NEXT:    s_add_i32 s1, s1, s5
+; GFX67-NEXT:    s_add_i32 s2, s2, s6
+; GFX67-NEXT:    s_add_i32 s3, s3, s7
+; GFX67-NEXT:    v_mov_b32_e32 v0, s0
+; GFX67-NEXT:    v_mov_b32_e32 v1, s1
+; GFX67-NEXT:    v_mov_b32_e32 v2, s2
+; GFX67-NEXT:    v_mov_b32_e32 v3, s3
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: load_v4i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s3, 0
+; GFX8-NEXT:    s_mov_b32 s2, s1
+; GFX8-NEXT:    s_mov_b32 s1, s3
+; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x20
+; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_add_i32 s0, s0, s4
+; GFX8-NEXT:    s_add_i32 s1, s1, s5
+; GFX8-NEXT:    s_add_i32 s2, s2, s6
+; GFX8-NEXT:    s_add_i32 s3, s3, s7
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_mov_b32_e32 v2, s2
+; GFX8-NEXT:    v_mov_b32_e32 v3, s3
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: load_v4i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, s1
+; GFX9-NEXT:    s_mov_b32 s3, 0
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x20
+; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_add_i32 s0, s8, s4
+; GFX9-NEXT:    s_add_i32 s1, s9, s5
+; GFX9-NEXT:    s_add_i32 s2, s10, s6
+; GFX9-NEXT:    s_add_i32 s3, s11, s7
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds <4 x i32>, ptr addrspace(6) %p1, i32 2
   %r0 = load <4 x i32>, ptr addrspace(6) %p0
   %r1 = load <4 x i32>, ptr addrspace(6) %gep1
@@ -61,17 +160,58 @@ define amdgpu_vs <4 x float> @load_v4i32(ptr addrspace(6) inreg %p0, ptr addrspa
   ret <4 x float> %r2
 }
 
-; GCN-LABEL: {{^}}load_v8i32:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x10
-; VI-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
-; GFX9-DAG: s_load_dwordx8 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx8 s[{{.*}}], s[2:3], 0x40
 define amdgpu_vs <8 x float> @load_v8i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v8i32:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx8 s[4:11], s[2:3], 0x10
+; GFX67-NEXT:    s_load_dwordx8 s[12:19], s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    s_add_i32 s0, s12, s4
+; GFX67-NEXT:    s_add_i32 s1, s13, s5
+; GFX67-NEXT:    s_add_i32 s2, s14, s6
+; GFX67-NEXT:    s_add_i32 s3, s15, s7
+; GFX67-NEXT:    s_add_i32 s4, s16, s8
+; GFX67-NEXT:    s_add_i32 s5, s17, s9
+; GFX67-NEXT:    s_add_i32 s6, s18, s10
+; GFX67-NEXT:    s_add_i32 s7, s19, s11
+; GFX67-NEXT:    v_mov_b32_e32 v0, s0
+; GFX67-NEXT:    v_mov_b32_e32 v1, s1
+; GFX67-NEXT:    v_mov_b32_e32 v2, s2
+; GFX67-NEXT:    v_mov_b32_e32 v3, s3
+; GFX67-NEXT:    v_mov_b32_e32 v4, s4
+; GFX67-NEXT:    v_mov_b32_e32 v5, s5
+; GFX67-NEXT:    v_mov_b32_e32 v6, s6
+; GFX67-NEXT:    v_mov_b32_e32 v7, s7
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX89-LABEL: load_v8i32:
+; GFX89:       ; %bb.0:
+; GFX89-NEXT:    s_mov_b32 s2, s1
+; GFX89-NEXT:    s_mov_b32 s3, 0
+; GFX89-NEXT:    s_mov_b32 s1, s3
+; GFX89-NEXT:    s_load_dwordx8 s[4:11], s[2:3], 0x40
+; GFX89-NEXT:    s_load_dwordx8 s[12:19], s[0:1], 0x0
+; GFX89-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX89-NEXT:    s_add_i32 s0, s12, s4
+; GFX89-NEXT:    s_add_i32 s1, s13, s5
+; GFX89-NEXT:    s_add_i32 s2, s14, s6
+; GFX89-NEXT:    s_add_i32 s3, s15, s7
+; GFX89-NEXT:    s_add_i32 s4, s16, s8
+; GFX89-NEXT:    s_add_i32 s5, s17, s9
+; GFX89-NEXT:    s_add_i32 s6, s18, s10
+; GFX89-NEXT:    s_add_i32 s7, s19, s11
+; GFX89-NEXT:    v_mov_b32_e32 v0, s0
+; GFX89-NEXT:    v_mov_b32_e32 v1, s1
+; GFX89-NEXT:    v_mov_b32_e32 v2, s2
+; GFX89-NEXT:    v_mov_b32_e32 v3, s3
+; GFX89-NEXT:    v_mov_b32_e32 v4, s4
+; GFX89-NEXT:    v_mov_b32_e32 v5, s5
+; GFX89-NEXT:    v_mov_b32_e32 v6, s6
+; GFX89-NEXT:    v_mov_b32_e32 v7, s7
+; GFX89-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds <8 x i32>, ptr addrspace(6) %p1, i32 2
   %r0 = load <8 x i32>, ptr addrspace(6) %p0
   %r1 = load <8 x i32>, ptr addrspace(6) %gep1
@@ -80,17 +220,90 @@ define amdgpu_vs <8 x float> @load_v8i32(ptr addrspace(6) inreg %p0, ptr addrspa
   ret <8 x float> %r2
 }
 
-; GCN-LABEL: {{^}}load_v16i32:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x20
-; VI-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
-; GFX9-DAG: s_load_dwordx16 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx16 s[{{.*}}], s[2:3], 0x80
 define amdgpu_vs <16 x float> @load_v16i32(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v16i32:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx16 s[4:19], s[2:3], 0x20
+; GFX67-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    s_add_i32 s0, s36, s4
+; GFX67-NEXT:    s_add_i32 s1, s37, s5
+; GFX67-NEXT:    s_add_i32 s2, s38, s6
+; GFX67-NEXT:    s_add_i32 s3, s39, s7
+; GFX67-NEXT:    s_add_i32 s4, s40, s8
+; GFX67-NEXT:    s_add_i32 s5, s41, s9
+; GFX67-NEXT:    s_add_i32 s6, s42, s10
+; GFX67-NEXT:    s_add_i32 s7, s43, s11
+; GFX67-NEXT:    s_add_i32 s8, s44, s12
+; GFX67-NEXT:    s_add_i32 s9, s45, s13
+; GFX67-NEXT:    s_add_i32 s10, s46, s14
+; GFX67-NEXT:    s_add_i32 s11, s47, s15
+; GFX67-NEXT:    s_add_i32 s12, s48, s16
+; GFX67-NEXT:    s_add_i32 s13, s49, s17
+; GFX67-NEXT:    s_add_i32 s14, s50, s18
+; GFX67-NEXT:    s_add_i32 s15, s51, s19
+; GFX67-NEXT:    v_mov_b32_e32 v0, s0
+; GFX67-NEXT:    v_mov_b32_e32 v1, s1
+; GFX67-NEXT:    v_mov_b32_e32 v2, s2
+; GFX67-NEXT:    v_mov_b32_e32 v3, s3
+; GFX67-NEXT:    v_mov_b32_e32 v4, s4
+; GFX67-NEXT:    v_mov_b32_e32 v5, s5
+; GFX67-NEXT:    v_mov_b32_e32 v6, s6
+; GFX67-NEXT:    v_mov_b32_e32 v7, s7
+; GFX67-NEXT:    v_mov_b32_e32 v8, s8
+; GFX67-NEXT:    v_mov_b32_e32 v9, s9
+; GFX67-NEXT:    v_mov_b32_e32 v10, s10
+; GFX67-NEXT:    v_mov_b32_e32 v11, s11
+; GFX67-NEXT:    v_mov_b32_e32 v12, s12
+; GFX67-NEXT:    v_mov_b32_e32 v13, s13
+; GFX67-NEXT:    v_mov_b32_e32 v14, s14
+; GFX67-NEXT:    v_mov_b32_e32 v15, s15
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX89-LABEL: load_v16i32:
+; GFX89:       ; %bb.0:
+; GFX89-NEXT:    s_mov_b32 s2, s1
+; GFX89-NEXT:    s_mov_b32 s3, 0
+; GFX89-NEXT:    s_mov_b32 s1, s3
+; GFX89-NEXT:    s_load_dwordx16 s[4:19], s[2:3], 0x80
+; GFX89-NEXT:    s_load_dwordx16 s[36:51], s[0:1], 0x0
+; GFX89-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX89-NEXT:    s_add_i32 s0, s36, s4
+; GFX89-NEXT:    s_add_i32 s1, s37, s5
+; GFX89-NEXT:    s_add_i32 s2, s38, s6
+; GFX89-NEXT:    s_add_i32 s3, s39, s7
+; GFX89-NEXT:    s_add_i32 s4, s40, s8
+; GFX89-NEXT:    s_add_i32 s5, s41, s9
+; GFX89-NEXT:    s_add_i32 s6, s42, s10
+; GFX89-NEXT:    s_add_i32 s7, s43, s11
+; GFX89-NEXT:    s_add_i32 s8, s44, s12
+; GFX89-NEXT:    s_add_i32 s9, s45, s13
+; GFX89-NEXT:    s_add_i32 s10, s46, s14
+; GFX89-NEXT:    s_add_i32 s11, s47, s15
+; GFX89-NEXT:    s_add_i32 s12, s48, s16
+; GFX89-NEXT:    s_add_i32 s13, s49, s17
+; GFX89-NEXT:    s_add_i32 s14, s50, s18
+; GFX89-NEXT:    s_add_i32 s15, s51, s19
+; GFX89-NEXT:    v_mov_b32_e32 v0, s0
+; GFX89-NEXT:    v_mov_b32_e32 v1, s1
+; GFX89-NEXT:    v_mov_b32_e32 v2, s2
+; GFX89-NEXT:    v_mov_b32_e32 v3, s3
+; GFX89-NEXT:    v_mov_b32_e32 v4, s4
+; GFX89-NEXT:    v_mov_b32_e32 v5, s5
+; GFX89-NEXT:    v_mov_b32_e32 v6, s6
+; GFX89-NEXT:    v_mov_b32_e32 v7, s7
+; GFX89-NEXT:    v_mov_b32_e32 v8, s8
+; GFX89-NEXT:    v_mov_b32_e32 v9, s9
+; GFX89-NEXT:    v_mov_b32_e32 v10, s10
+; GFX89-NEXT:    v_mov_b32_e32 v11, s11
+; GFX89-NEXT:    v_mov_b32_e32 v12, s12
+; GFX89-NEXT:    v_mov_b32_e32 v13, s13
+; GFX89-NEXT:    v_mov_b32_e32 v14, s14
+; GFX89-NEXT:    v_mov_b32_e32 v15, s15
+; GFX89-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds <16 x i32>, ptr addrspace(6) %p1, i32 2
   %r0 = load <16 x i32>, ptr addrspace(6) %p0
   %r1 = load <16 x i32>, ptr addrspace(6) %gep1
@@ -99,17 +312,42 @@ define amdgpu_vs <16 x float> @load_v16i32(ptr addrspace(6) inreg %p0, ptr addrs
   ret <16 x float> %r2
 }
 
-; GCN-LABEL: {{^}}load_float:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
-; SICI-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x2
-; VI-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
-; VI-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
-; GFX9-DAG: s_load_dword s{{[0-9]}}, s[0:1], 0x0
-; GFX9-DAG: s_load_dword s{{[0-9]}}, s[2:3], 0x8
 define amdgpu_vs float @load_float(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_float:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dword s2, s[2:3], 0x2
+; GFX67-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    v_mov_b32_e32 v0, s2
+; GFX67-NEXT:    v_add_f32_e32 v0, s0, v0
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: load_float:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s2, s1
+; GFX8-NEXT:    s_mov_b32 s3, 0
+; GFX8-NEXT:    s_mov_b32 s1, s3
+; GFX8-NEXT:    s_load_dword s2, s[2:3], 0x8
+; GFX8-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v0, s2
+; GFX8-NEXT:    v_add_f32_e32 v0, s0, v0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: load_float:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, s1
+; GFX9-NEXT:    s_mov_b32 s3, 0
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_load_dword s4, s[2:3], 0x8
+; GFX9-NEXT:    s_load_dword s5, s[0:1], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_add_f32_e32 v0, s5, v0
+; GFX9-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds float, ptr addrspace(6) %p1, i32 2
   %r0 = load float, ptr addrspace(6) %p0
   %r1 = load float, ptr addrspace(6) %gep1
@@ -117,20 +355,48 @@ define amdgpu_vs float @load_float(ptr addrspace(6) inreg %p0, ptr addrspace(6)
   ret float %r
 }
 
-; GCN-LABEL: {{^}}load_v2float:
-; SICIVI-DAG: s_mov_b32 s3, 0
-; SICIVI-DAG: s_mov_b32 s2, s1
-; SICIVI-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x4
-; VI-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
-; GFX9-DAG: s_mov_b32 s2, s1
-; GFX9-DAG: s_mov_b32 s3, 0
-; GFX9-DAG: s_mov_b32 s1, s3
-; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx2 s[{{.*}}], s[2:3], 0x10
 define amdgpu_vs <2 x float> @load_v2float(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v2float:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x4
+; GFX67-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX67-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX67-NEXT:    v_mov_b32_e32 v0, s2
+; GFX67-NEXT:    v_mov_b32_e32 v1, s3
+; GFX67-NEXT:    v_add_f32_e32 v0, s0, v0
+; GFX67-NEXT:    v_add_f32_e32 v1, s1, v1
+; GFX67-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: load_v2float:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_mov_b32 s3, 0
+; GFX8-NEXT:    s_mov_b32 s2, s1
+; GFX8-NEXT:    s_mov_b32 s1, s3
+; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x10
+; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v0, s2
+; GFX8-NEXT:    v_mov_b32_e32 v1, s3
+; GFX8-NEXT:    v_add_f32_e32 v0, s0, v0
+; GFX8-NEXT:    v_add_f32_e32 v1, s1, v1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: load_v2float:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_mov_b32 s2, s1
+; GFX9-NEXT:    s_mov_b32 s3, 0
+; GFX9-NEXT:    s_mov_b32 s1, s3
+; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x10
+; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_add_f32_e32 v0, s6, v0
+; GFX9-NEXT:    v_add_f32_e32 v1, s7, v1
+; GFX9-NEXT:    ; return to shader part epilog
   %gep1 = getelementptr inbounds <2 x float>, ptr addrspace(6) %p1, i32 2
   %r0 = load <2 x float>, ptr addrspace(6) %p0
   %r1 = load <2 x float>, ptr addrspace(6) %gep1
@@ -138,17 +404,60 @@ define amdgpu_vs <2 x float> @load_v2float(ptr addrspace(6) inreg %p0, ptr addrs
   ret <2 x float> %r
 }
 
-; GCN-LABEL: {{^}}load_v4float:
-; GCN-DAG: s_mov_b32 s3, 0
-; GCN-DAG: s_mov_b32 s2, s1
-; GCN-DAG: s_mov_b32 s1, s3
-; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
-; VI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; VI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
-; GFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
-; GFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
 define amdgpu_vs <4 x float> @load_v4float(ptr addrspace(6) inreg %p0, ptr addrspace(6) inreg %p1) #0 {
+; GFX67-LABEL: load_v4float:
+; GFX67:       ; %bb.0:
+; GFX67-NEXT:    s_mov_b32 s3, 0
+; GFX67-NEXT:    s_mov_b32 s2, s1
+; GFX67-NEXT:    s_mov_b32 s1, s3
+; GFX67-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x8
+; GFX67-NEXT:    s_load_dwordx4 s[0:3], s[0:1]...
[truncated]

@arsenm arsenm marked this pull request as ready for review November 21, 2025 00:10
@arsenm arsenm mentioned this pull request Nov 21, 2025
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@arsenm arsenm merged commit 3954df9 into main Nov 21, 2025
11 of 13 checks passed
@arsenm arsenm deleted the users/arsenm/amdgpu/convert-constant-address-space-32-bit-test-generated-checks branch November 21, 2025 00:45
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llvm-ci commented Nov 21, 2025

LLVM Buildbot has detected a new failure on builder ppc64le-flang-rhel-clang running on ppc64le-flang-rhel-test while building llvm at step 6 "test-build-unified-tree-check-flang".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/157/builds/42397

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-flang) failure: 1200 seconds without output running [b'ninja', b'check-flang'], attempting to kill
59.810 [4/29/0] cd /home/buildbots/llvm-external-buildbots/workers/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/runtimes/runtimes-bins && /home/buildbots/llvm-external-buildbots/cmake-3.31.2/bin/cmake --build /home/buildbots/llvm-external-buildbots/workers/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/runtimes/runtimes-bins/ --target libomp-mod --config Release
ninja: no work to do.
60.877 [2/5/27] Building CXX object tools/flang/unittests/Optimizer/CMakeFiles/FlangOptimizerTests.dir/FortranVariableTest.cpp.o
61.257 [2/3/29] Building CXX object tools/flang/unittests/Optimizer/CMakeFiles/FlangOptimizerTests.dir/RTBuilder.cpp.o
62.829 [1/3/30] Linking CXX executable tools/flang/unittests/Common/FlangCommonTests
82.903 [1/2/31] Linking CXX executable tools/flang/unittests/Optimizer/FlangOptimizerTests
120.305 [1/1/32] Linking CXX executable tools/flang/unittests/Frontend/FlangFrontendTests
120.307 [0/1/32] Running the Flang regression tests
command timed out: 1200 seconds without output running [b'ninja', b'check-flang'], attempting to kill
process killed by signal 9
program finished with exit code -1
elapsedTime=1323.138644

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