Skip to content

Conversation

@justinfargnoli
Copy link
Contributor

The operand types of a mul.wide are half the size of the output type. combineMulWide incorrectly uses the output type of the mul.wide for the operand type.

Copy link
Contributor

Copilot AI left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Pull Request Overview

This PR fixes a type mismatch in the NVPTX backend's combineMulWide function. The mul.wide instruction requires operands that are half the size of the output type, but the code was incorrectly using the output type (ToVT) instead of the operand type (FromVT) when creating constant operands for shift-to-multiply transformations.

Key Changes:

  • Corrected the bit width used when creating APInt constants from ToVT.getSizeInBits() to FromVT.getSizeInBits()
  • Updated the type parameter in getConstant() from ToVT to FromVT

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

@llvmbot
Copy link
Member

llvmbot commented Nov 21, 2025

@llvm/pr-subscribers-backend-nvptx

Author: Justin Fargnoli (justinfargnoli)

Changes

The operand types of a mul.wide are half the size of the output type. combineMulWide incorrectly uses the output type of the mul.wide for the operand type.


Full diff: https://github.com/llvm/llvm-project/pull/168986.diff

1 Files Affected:

  • (modified) llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp (+2-2)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index a77eb0240e677..b843b8344d15c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -5695,8 +5695,8 @@ static SDValue combineMulWide(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   SDValue RHS = Op.getOperand(1);
   if (Op.getOpcode() == ISD::SHL) {
     const auto ShiftAmt = Op.getConstantOperandVal(1);
-    const auto MulVal = APInt(ToVT.getSizeInBits(), 1) << ShiftAmt;
-    RHS = DCI.DAG.getConstant(MulVal, DL, ToVT);
+    const auto MulVal = APInt(FromVT.getSizeInBits(), 1) << ShiftAmt;
+    RHS = DCI.DAG.getConstant(MulVal, DL, FromVT);
   }
   return DCI.DAG.getNode(Opcode, DL, ToVT, Op.getOperand(0), RHS);
 }

@justinfargnoli
Copy link
Contributor Author

I don't have a test case that exposes this bug. I discovered this while prototyping another change. Since I'm not sure when that prototype will be ready for review, or whether it makes sense to land at all, I wanted to put up a fix and expose that this bug exists.

@justinfargnoli justinfargnoli changed the title [NVPTX] Fix mul.wide operand type when matching on shl in combineMulWide [NVPTX] Use correct mul.wide operand type when matching on shl in combineMulWide Nov 21, 2025
@github-actions
Copy link

🐧 Linux x64 Test Results

  • 186431 tests passed
  • 4864 tests skipped

Copy link
Member

@AlexMaclean AlexMaclean left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

Comment on lines +5698 to +5699
const auto MulVal = APInt(FromVT.getSizeInBits(), 1) << ShiftAmt;
RHS = DCI.DAG.getConstant(MulVal, DL, FromVT);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It would be great to add a test that would catch such a mismatch.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants