[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG.

[topperc]

I think we need to keep the SelectionDAG code for volatile load/store so we should support 4 byte alignment when possible.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

I think we need to keep the SelectionDAG code for volatile load/store so we should support 4 byte alignment when possible.

---

Full diff: https://github.com/llvm/llvm-project/pull/169182.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+7)
• (modified) llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp (+1-3)

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 29df53c6c9893..b659bb96f2f11 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -237,6 +237,13 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 
     return 0;
   }
+
+  Align getZilsdAlign() const {
+    return Align(enableUnalignedScalarMem() ? 1
+                 : allowZilsd4ByteAlign()   ? 4
+                                            : 8);
+  }
+
   unsigned getELen() const {
     assert(hasVInstructions() && "Expected V extension");
     return hasVInstructionsI64() ? 64 : 32;
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 99e83fbb05a73..3b47903c351bf 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -146,9 +146,7 @@ bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
 
   // Check alignment: default is 8-byte, but allow 4-byte with tune feature
   // If unaligned scalar memory is enabled, allow any alignment
-  RequiredAlign = STI->enableUnalignedScalarMem() ? Align(1)
-                  : STI->allowZilsd4ByteAlign()   ? Align(4)
-                                                  : Align(8);
+  RequiredAlign = STI->getZilsdAlign();
   bool Modified = false;
   for (auto &MBB : MF) {
     Modified |= rescheduleLoadStoreInstrs(&MBB);

[lenary]

Did you leave out the SDag changes? This is just a Subtarget change right now.

[topperc]

Did you leave out the SDag changes? This is just a Subtarget change right now.

Weird. I wrote a SelectionDAG change and a test. I don't know where they went.

[lenary]

LGTM

[4vtomat]

LGTM~

[4vtomat]

do we also want to handle non-volatile case in selection dag?