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[X86] X86ISelDAGToDAG - don't let ADD/SUB(X,1) -> SUB/ADD(X,-1) constant fold #169217
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…ant fold Extension to llvm#168726 - ensure we peek through bitcasts to look for constants (as constant folding will) Fixes llvm#169205
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesExtension to #168726 - ensure we peek through bitcasts to look for constants (as constant folding will) DAG should have constant folded this, but we're still fighting the lack of proper topological sorting. Fixes #169205 Full diff: https://github.com/llvm/llvm-project/pull/169217.diff 2 Files Affected:
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 2b5a63aa66926..e7903a72d85bb 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1004,7 +1004,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
if ((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
N->getSimpleValueType(0).isVector() && !mayPreventLoadFold()) {
APInt SplatVal;
- if (!ISD::isBuildVectorOfConstantSDNodes(N->getOperand(0).getNode()) &&
+ if (!ISD::isBuildVectorOfConstantSDNodes(
+ peekThroughBitcasts(N->getOperand(0)).getNode()) &&
X86::isConstantSplat(N->getOperand(1), SplatVal) &&
SplatVal.isOne()) {
SDLoc DL(N);
diff --git a/llvm/test/CodeGen/X86/pr169205.ll b/llvm/test/CodeGen/X86/pr169205.ll
new file mode 100644
index 0000000000000..1416102d6ba77
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr169205.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
+
+define <4 x i16> @PR169205() {
+; SSE-LABEL: PR169205:
+; SSE: # %bb.0:
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,1,1,1,u,u,u,u]
+; SSE-NEXT: retq
+;
+; AVX-LABEL: PR169205:
+; AVX: # %bb.0:
+; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: retq
+ %avg = tail call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer)
+ %shuffle24 = shufflevector <16 x i8> %avg, <16 x i8> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 9, i32 9>
+ %conv25 = zext <4 x i8> %shuffle24 to <4 x i16>
+ %not.neg = add <4 x i16> %conv25, splat (i16 1)
+ ret <4 x i16> %not.neg
+}
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/187/builds/13883 Here is the relevant piece of the build log for the reference |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/54/builds/14951 Here is the relevant piece of the build log for the reference |
Extension to #168726 - ensure we peek through bitcasts to look for constants (as constant folding will)
DAG should have constant folded this, but we're still fighting the lack of proper topological sorting.
Fixes #169205