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[AMDGPU] Reland "Remove leftover implicit operands from SI_SPILL/SI_RESTORE" #169449

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[AMDGPU] Reland "Remove leftover implicit operands from SI_SPILL/SI_RESTORE" #169449

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@LU-JOHN LU-JOHN commented Nov 25, 2025 •
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Reland #168546. Update kill and undef flags to satisfy MachineVerifier. PR was reverted in #169068.

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llvmbot commented Nov 25, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: None (LU-JOHN)

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Reland #168546. Update kill and undef flags to satisfy MachineVerifier.

Patch is 167.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/169449.diff

15 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+12-2)
  • (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+636-636)
  • (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+31-31)
  • (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll (+1-1)
  • (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir (+12-12)
  • (modified) llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll (+19-19)
  • (modified) llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll (+3-3)
  • (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll (+20-20)
  • (modified) llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll (+22-22)
  • (modified) llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll (+4-4)
  • (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll (-1)
  • (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved.ll (-2)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index a7333e3373f38..27c39933dc682 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2094,11 +2094,21 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     break;
 
   case AMDGPU::SI_SPILL_S32_TO_VGPR:
-    MI.setDesc(get(AMDGPU::V_WRITELANE_B32));
+    mutateAndCleanupImplicit(MI, get(AMDGPU::V_WRITELANE_B32));
+    // When leftover implicit-def operands are removed, kill flag is no longer
+    // valid.  Thus:
+    //   $X = SI_SPILL_S32_TO_VGPR killed $sgpr0, 0, $X(tied-def 0),
+    //   implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1
+    // must be converted to:
+    //   $X = V_WRITELANE_B32 $sgpr0, 0, $X(tied-def 0)
+    MI.getOperand(1).setIsKill(false);
+    // Sometimes a SGPR that has already been killed is spilled.
+    // Add undef to appease the MachineVerifier.
+    MI.getOperand(1).setIsUndef(true);
     break;
 
   case AMDGPU::SI_RESTORE_S32_FROM_VGPR:
-    MI.setDesc(get(AMDGPU::V_READLANE_B32));
+    mutateAndCleanupImplicit(MI, get(AMDGPU::V_READLANE_B32));
     break;
   case AMDGPU::AV_MOV_B32_IMM_PSEUDO: {
     Register Dst = MI.getOperand(0).getReg();
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 4c5c56a49fdc6..4519e2796fed3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -8181,8 +8181,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s18
 ; SI-NEXT:    v_readlane_b32 s18, v23, 0
 ; SI-NEXT:    s_and_b32 s16, s16, 0xff
-; SI-NEXT:    v_readlane_b32 s19, v23, 1
 ; SI-NEXT:    s_lshl_b32 s18, s18, 8
+; SI-NEXT:    v_readlane_b32 s19, v23, 1
 ; SI-NEXT:    s_or_b32 s16, s16, s18
 ; SI-NEXT:    v_readlane_b32 s18, v23, 2
 ; SI-NEXT:    v_readlane_b32 s19, v23, 3
@@ -8215,8 +8215,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s16
 ; SI-NEXT:    v_readlane_b32 s16, v23, 6
 ; SI-NEXT:    s_and_b32 s14, s14, 0xff
-; SI-NEXT:    v_readlane_b32 s17, v23, 7
 ; SI-NEXT:    s_lshl_b32 s16, s16, 8
+; SI-NEXT:    v_readlane_b32 s17, v23, 7
 ; SI-NEXT:    s_or_b32 s14, s14, s16
 ; SI-NEXT:    v_readlane_b32 s16, v23, 8
 ; SI-NEXT:    v_readlane_b32 s17, v23, 9
@@ -8249,8 +8249,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s14
 ; SI-NEXT:    v_readlane_b32 s14, v23, 12
 ; SI-NEXT:    s_and_b32 s12, s12, 0xff
-; SI-NEXT:    v_readlane_b32 s15, v23, 13
 ; SI-NEXT:    s_lshl_b32 s14, s14, 8
+; SI-NEXT:    v_readlane_b32 s15, v23, 13
 ; SI-NEXT:    s_or_b32 s12, s12, s14
 ; SI-NEXT:    v_readlane_b32 s14, v23, 14
 ; SI-NEXT:    v_readlane_b32 s15, v23, 15
@@ -8283,8 +8283,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s12
 ; SI-NEXT:    v_readlane_b32 s12, v23, 18
 ; SI-NEXT:    s_and_b32 s10, s10, 0xff
-; SI-NEXT:    v_readlane_b32 s13, v23, 19
 ; SI-NEXT:    s_lshl_b32 s12, s12, 8
+; SI-NEXT:    v_readlane_b32 s13, v23, 19
 ; SI-NEXT:    s_or_b32 s10, s10, s12
 ; SI-NEXT:    v_readlane_b32 s12, v23, 20
 ; SI-NEXT:    v_readlane_b32 s13, v23, 21
@@ -8317,8 +8317,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s10
 ; SI-NEXT:    v_readlane_b32 s10, v23, 24
 ; SI-NEXT:    s_and_b32 s8, s8, 0xff
-; SI-NEXT:    v_readlane_b32 s11, v23, 25
 ; SI-NEXT:    s_lshl_b32 s10, s10, 8
+; SI-NEXT:    v_readlane_b32 s11, v23, 25
 ; SI-NEXT:    s_or_b32 s8, s8, s10
 ; SI-NEXT:    v_readlane_b32 s10, v23, 26
 ; SI-NEXT:    v_readlane_b32 s11, v23, 27
@@ -8350,8 +8350,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s8
 ; SI-NEXT:    v_readlane_b32 s8, v23, 30
 ; SI-NEXT:    s_and_b32 s6, s6, 0xff
-; SI-NEXT:    v_readlane_b32 s9, v23, 31
 ; SI-NEXT:    s_lshl_b32 s8, s8, 8
+; SI-NEXT:    v_readlane_b32 s9, v23, 31
 ; SI-NEXT:    s_or_b32 s6, s6, s8
 ; SI-NEXT:    v_readlane_b32 s8, v23, 32
 ; SI-NEXT:    v_readlane_b32 s9, v23, 33
@@ -8384,8 +8384,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    v_mov_b32_e32 v2, s6
 ; SI-NEXT:    v_readlane_b32 s6, v23, 36
 ; SI-NEXT:    s_and_b32 s4, s4, 0xff
-; SI-NEXT:    v_readlane_b32 s7, v23, 37
 ; SI-NEXT:    s_lshl_b32 s6, s6, 8
+; SI-NEXT:    v_readlane_b32 s7, v23, 37
 ; SI-NEXT:    s_or_b32 s4, s4, s6
 ; SI-NEXT:    v_readlane_b32 s6, v23, 38
 ; SI-NEXT:    v_readlane_b32 s7, v23, 39
@@ -8468,148 +8468,149 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ; SI-NEXT:  .LBB13_4:
-; SI-NEXT:    ; implicit-def: $sgpr51
 ; SI-NEXT:    ; implicit-def: $sgpr50
-; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    s_waitcnt expcnt(0)
 ; SI-NEXT:    v_writelane_b32 v23, s50, 0
-; SI-NEXT:    v_writelane_b32 v23, s51, 1
-; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    ; implicit-def: $sgpr51
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 1
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 2
-; SI-NEXT:    v_writelane_b32 v23, s51, 3
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 2
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 3
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 4
-; SI-NEXT:    v_writelane_b32 v23, s51, 5
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 4
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 5
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 6
-; SI-NEXT:    v_writelane_b32 v23, s51, 7
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 6
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 7
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 8
-; SI-NEXT:    v_writelane_b32 v23, s51, 9
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 8
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 9
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 10
-; SI-NEXT:    v_writelane_b32 v23, s51, 11
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 10
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 11
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 12
-; SI-NEXT:    v_writelane_b32 v23, s51, 13
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 12
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 13
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 14
-; SI-NEXT:    v_writelane_b32 v23, s51, 15
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 14
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 15
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 16
-; SI-NEXT:    v_writelane_b32 v23, s51, 17
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 16
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 17
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 18
-; SI-NEXT:    v_writelane_b32 v23, s51, 19
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 18
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 19
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 20
-; SI-NEXT:    v_writelane_b32 v23, s51, 21
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 20
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 21
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 22
-; SI-NEXT:    v_writelane_b32 v23, s51, 23
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 22
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 23
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 24
-; SI-NEXT:    v_writelane_b32 v23, s51, 25
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 24
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 25
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 26
-; SI-NEXT:    v_writelane_b32 v23, s51, 27
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 26
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 27
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 28
-; SI-NEXT:    v_writelane_b32 v23, s51, 29
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 28
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 29
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 30
-; SI-NEXT:    v_writelane_b32 v23, s51, 31
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 30
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 31
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 32
-; SI-NEXT:    v_writelane_b32 v23, s51, 33
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 32
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 33
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 34
-; SI-NEXT:    v_writelane_b32 v23, s51, 35
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 34
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 35
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 36
-; SI-NEXT:    v_writelane_b32 v23, s51, 37
 ; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 36
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    v_writelane_b32 v23, s51, 37
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    ; implicit-def: $sgpr50
 ; SI-NEXT:    v_writelane_b32 v23, s50, 38
+; SI-NEXT:    ; kill: killed $sgpr26
+; SI-NEXT:    ; implicit-def: $sgpr26
 ; SI-NEXT:    v_writelane_b32 v23, s51, 39
-; SI-NEXT:    ; implicit-def: $sgpr50
 ; SI-NEXT:    ; kill: killed $sgpr26
 ; SI-NEXT:    ; implicit-def: $sgpr26
+; SI-NEXT:    ; implicit-def: $sgpr50
+; SI-NEXT:    v_writelane_b32 v23, s50, 40
 ; SI-NEXT:    ; implicit-def: $sgpr49
 ; SI-NEXT:    ; implicit-def: $sgpr55
 ; SI-NEXT:    ; implicit-def: $sgpr54
@@ -8634,7 +8635,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; SI-NEXT:    ; implicit-def: $sgpr58
 ; SI-NEXT:    ; implicit-def: $sgpr28
 ; SI-NEXT:    ; implicit-def: $sgpr26
-; SI-NEXT:    v_writelane_b32 v23, s50, 40
 ; SI-NEXT:    ; implicit-def: $sgpr98
 ; SI-NEXT:    ; implicit-def: $sgpr96
 ; SI-NEXT:    ; implicit-def: $sgpr86
@@ -10597,10 +10597,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX9-NEXT:  .LBB13_4:
 ; GFX9-NEXT:    ; implicit-def: $sgpr27
 ; GFX9-NEXT:    ; kill: killed $sgpr27
-; GFX9-NEXT:    ; implicit-def: $sgpr83
-; GFX9-NEXT:    ; implicit-def: $sgpr82
 ; GFX9-NEXT:    ; implicit-def: $sgpr27
 ; GFX9-NEXT:    ; kill: killed $sgpr27
+; GFX9-NEXT:    ; implicit-def: $sgpr82
 ; GFX9-NEXT:    v_writelane_b32 v22, s82, 0
 ; GFX9-NEXT:    ; implicit-def: $sgpr27
 ; GFX9-NEXT:    ; kill: killed $sgpr27
@@ -10633,6 +10632,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX9-NEXT:    ; implicit-def: $sgpr85
 ; GFX9-NEXT:    ; implicit-def: $sgpr84
 ; GFX9-NEXT:    ; implicit-def: $sgpr81
+; GFX9-NEXT:    ; implicit-def: $sgpr83
 ; GFX9-NEXT:    ; implicit-def: $sgpr36
 ; GFX9-NEXT:    ; implicit-def: $sgpr34
 ; GFX9-NEXT:    ; implicit-def: $sgpr30
@@ -10985,12 +10985,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    s_lshr_b64 s[62:63], s[20:21], 24
 ; GFX11-NEXT:    s_branch .LBB13_3
 ; GFX11-NEXT:  .LBB13_2:
-; GFX11-NEXT:    ; implicit-def: $vcc_hi
 ; GFX11-NEXT:    ; implicit-def: $vcc_lo
-; GFX11-NEXT:    ; implicit-def: $sgpr42
-; GFX11-NEXT:    ; kill: killed $sgpr42
-; GFX11-NEXT:    s_mov_b32 s101, -1
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 0
+; GFX11-NEXT:    ; implicit-def: $vcc_hi
+; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
@@ -11001,7 +10999,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 1
-; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
@@ -11013,6 +11010,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 2
+; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
@@ -11024,7 +11022,6 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 3
-; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
@@ -11036,6 +11033,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 4
+; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
@@ -11044,10 +11042,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
+; GFX11-NEXT:    s_mov_b32 s101, -1
+; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 5
+; GFX11-NEXT:    ; kill: killed $sgpr42
+; GFX11-NEXT:    ; implicit-def: $sgpr42
 ; GFX11-NEXT:    ; kill: killed $sgpr42
 ; GFX11-NEXT:    ; implicit-def: $sgpr42
-; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 5
-; GFX11-NEXT:    ; implicit-def: $vcc_lo
 ; GFX11-NEXT:    ; implicit-def: $sgpr45
 ; GFX11-NEXT:    ; implicit-def: $sgpr44
 ; GFX11-NEXT:    ; implicit-def: $sgpr30
@@ -11111,17 +11111,17 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
 ; GFX11-NEXT:    ; implicit-def: $sgpr88
 ; GFX11-NEXT:    ; implicit-def: $sgpr76
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 6
-; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 7
 ; GFX11-NEXT:    ; implicit-def: $vcc_lo
+; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 7
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 8
-; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 9
 ; GFX11-NEXT:    ; implicit-def: $vcc_lo
+; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 9
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 10
-; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 11
 ; GFX11-NEXT:    ; implicit-def: $vcc_lo
+; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 11
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 12
-; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 13
 ; GFX11-NEXT:    ; implicit-def: $vcc_lo
+; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 13
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_lo, 14
 ; GFX11-NEXT:    v_writelane_b32 v37, vcc_hi, 15
 ; GFX11-NEXT:  .LBB13_3: ; %Flow
@@ -44444,147 +44444,149 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
 ; SI-NEXT:    v_lshrrev_b32_e32 v10, 8, v37
 ; SI-NEXT:    s_branch .LBB37_5
 ; SI-NEXT:  .LBB37_3:
-; SI-NEXT:    ; implicit-def: $sgpr61
 ; SI-NEXT:    ; implicit-def: $sgpr60
-; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    v_writelane_b32 v61, s60, 0
+; SI-NEXT:    ; implicit-def: $sgpr61
 ; SI-NEXT:    v_writelane_b32 v61, s61, 1
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, s60, 2
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    v_writelane_b32 v61, s60, 2
 ; SI-NEXT:    v_writelane_b32 v61, s61, 3
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, s60, 4
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    v_writelane_b32 v61, s60, 4
 ; SI-NEXT:    v_writelane_b32 v61, s61, 5
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, s60, 6
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    v_writelane_b32 v61, s60, 6
 ; SI-NEXT:    v_writelane_b32 v61, s61, 7
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, s60, 8
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    v_writelane_b32 v61, s60, 8
 ; SI-NEXT:    v_writelane_b32 v61, s61, 9
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, s60, 10
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
-; SI-NEXT:    v_writelane_b32 v61, s60, 10
 ; SI-NEXT:    v_writelane_b32 v61, s61, 11
-; SI-NEXT:    ; implicit-def: $sgpr60
 ; SI-NEXT:    ; kill: killed $sgpr4
 ; SI-NEXT:    ; implicit-def: $sgpr4
+; SI-NEXT:    ; implicit-def: $sgpr60
+; SI-NEXT:    v_writelane_b32 v61, ...
[truncated]

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github-actions bot commented Nov 25, 2025

⚠️ undef deprecator found issues in your code. ⚠️

You can test this locally with the following command: 
git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef([^a-zA-Z0-9_-]|$)|UndefValue::get)' 'HEAD~1' HEAD llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll llvm/test/CodeGen/AMDGPU/load-constant-i1.ll llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

The following files introduce new uses of undef:

  • llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll

Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields undef. You should use poison values for placeholders instead.

In tests, avoid using undef and having tests that trigger undefined behavior. If you need an operand with some unimportant value, you can add a new argument to the function and use that instead.

For example, this is considered a bad practice:

define void @fn() {
  ...
  br i1 undef, ...
}

Please use the following instead:

define void @fn(i1 %cond) {
  ...
  br i1 %cond, ...
}

Please refer to the Undefined Behavior Manual for more information.

arsenm
arsenm reviewed Nov 25, 2025
View reviewed changes
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
// implicit-def $sgpr0_sgpr1, implicit $sgpr0_sgpr1
// must be converted to:
// $X = V_WRITELANE_B32 $sgpr0, 0, $X(tied-def 0)
MI.getOperand(1).setIsKill(false);
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@arsenm arsenm Nov 25, 2025

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This part seems plausible

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@LU-JOHN LU-JOHN Nov 26, 2025

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Tested in invalid-kill.mir.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Comment on lines +2105 to +2107
// Sometimes a SGPR that has already been killed is spilled.
// Add undef to appease the MachineVerifier.
MI.getOperand(1).setIsUndef(true);
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@arsenm arsenm Nov 25, 2025

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This part does not. Can you add mir test function for these cases

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@LU-JOHN LU-JOHN Nov 26, 2025

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Tested in spilled-kill.mir.

@LU-JOHN
Add testcase that spills a killed register
4e86066 
Signed-off-by: John Lu <John.Lu@amd.com>
@LU-JOHN
Minimize testcase
91a4367 
Signed-off-by: John Lu <John.Lu@amd.com>
@LU-JOHN
Test necessity of removing kill flag.
682267d 
Signed-off-by: John Lu <John.Lu@amd.com>
@LU-JOHN LU-JOHN requested a review from arsenm November 26, 2025 00:21
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