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[Exegesis][RISCV] Support C_LDSP for llvm-exegesis #169660

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Merged
sunshaoce merged 4 commits into from
Dec 4, 2025
Merged

[Exegesis][RISCV] Support C_LDSP for llvm-exegesis #169660

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a8fdd09
[Exegesis][RISCV] Support C_LDSP for llvm-exegesis
sunshaoce Nov 26, 2025
aba68de
update test
sunshaoce Nov 26, 2025
624a2c7
fixup! override rd in fillMemoryOperands
sunshaoce Dec 1, 2025
525c095
Address comments
sunshaoce Dec 4, 2025
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9 changes: 9 additions & 0 deletions llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
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Original file line number Diff line number Diff line change
Expand Up @@ -46,3 +46,12 @@ C_SRLI-NEXT: key:
C_SRLI-NEXT: instructions:
C_SRLI-NEXT: - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
C_SRLI-DAG: ...

# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_LDSP -mattr=+c | FileCheck --check-prefix=C_LDSP %s

C_LDSP: ---
C_LDSP-NEXT: mode: latency
C_LDSP-NEXT: key:
C_LDSP-NEXT: instructions:
C_LDSP-NEXT: - 'C_LDSP X2 X2 [[IMM11:i_0x[0-9]+]]'
C_LDSP-DAG: ...
9 changes: 9 additions & 0 deletions llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
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Expand Up @@ -819,6 +819,15 @@ void ExegesisRISCVTarget::fillMemoryOperands(InstructionTemplate &IT,

assert(MemOp.isReg() && "Memory operand expected to be register");

unsigned Opcode = I.getOpcode();
if (Opcode == RISCV::C_LDSP || Opcode == RISCV::C_LWSP ||
Opcode == RISCV::C_SDSP || Opcode == RISCV::C_SWSP) {
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@topperc topperc Nov 26, 2025

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Do we need to do the FP versions too?

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@sunshaoce sunshaoce Nov 26, 2025

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I tested some instructions, but none of them can be measured:

C_FLDSP: No strategy found to make the execution serial
C_FSDSP: No strategy found to make the execution serial
C_FLWSP: No strategy found to make the execution serial
C_FSWSP: No strategy found to make the execution serial

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@mshockwave mshockwave Nov 26, 2025

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In C_LDSP's case, it'll try to create an alias between the destination register of the previous load to the base register of the following instruction, which is always X2. But when it comes to C_FLDSP the same trick doesn't work because now the desination register is a floating point register, which is incompatible with X2.

IT.getValueFor(I.Operands[0]) = MCOperand::createReg(RISCV::X2);
// Force base register to SP (X2)
IT.getValueFor(MemOp) = MCOperand::createReg(RISCV::X2);
return;
}

IT.getValueFor(MemOp) = MCOperand::createReg(Reg);
}

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7 changes: 6 additions & 1 deletion llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
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Expand Up @@ -142,7 +142,12 @@ static void appendCodeTemplates(const LLVMState &State,
return;

ET.fillMemoryOperands(Variant, ScratchMemoryRegister, 0);
Variant.getValueFor(DefOp) = MCOperand::createReg(ScratchMemoryRegister);

// Only force the def register to ScratchMemoryRegister if the target
// hasn't assigned a value yet.
MCOperand &DefVal = Variant.getValueFor(DefOp);
if (!DefVal.isValid())
DefVal = MCOperand::createReg(ScratchMemoryRegister);

CodeTemplate CT;
CT.Execution = ExecutionModeBit;
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