[X86][APX] Compress setzucc with memory operand to setcc #170842
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setzucc with memory operand is same as setcc but the later is shorter.
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-backend-x86 Author: Feng Zou (fzou1) Changessetzucc with memory operand is same as setcc but the later is shorter. Full diff: https://github.com/llvm/llvm-project/pull/170842.diff 5 Files Affected:
diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp
index ddbd10d8f7eda..570dd951da96c 100644
--- a/llvm/lib/Target/X86/X86CompressEVEX.cpp
+++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp
@@ -15,6 +15,7 @@
// c. NDD (EVEX) -> non-NDD (legacy)
// d. NF_ND (EVEX) -> NF (EVEX)
// e. NonNF (EVEX) -> NF (EVEX)
+// f. SETZUCCm (EVEX) -> SETCCm
//
// Compression a, b and c can always reduce code size, with some exceptions
// such as promoted 16-bit CRC32 which is as long as the legacy version.
@@ -216,14 +217,15 @@ static bool CompressEVEXImpl(MachineInstr &MI, MachineBasicBlock &MBB,
// memory form: broadcast
//
// APX:
- // MAP4: NDD
+ // MAP4: NDD, ZU
//
// For AVX512 cases, EVEX prefix is needed in order to carry this information
// thus preventing the transformation to VEX encoding.
bool IsND = X86II::hasNewDataDest(TSFlags);
- if (TSFlags & X86II::EVEX_B && !IsND)
- return false;
unsigned Opc = MI.getOpcode();
+ bool IsSetZUCCm = Opc == X86::SETZUCCm;
+ if (TSFlags & X86II::EVEX_B && !IsND && !IsSetZUCCm)
+ return false;
// MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
bool IsRedundantNDD = IsNDLike ? IsRedundantNewDataDest(Opc) : false;
@@ -339,7 +341,7 @@ bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) {
}
#endif
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
- if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD())
+ if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD() && !ST.hasZU())
return false;
bool Changed = false;
diff --git a/llvm/test/CodeGen/X86/apx/compress-evex.mir b/llvm/test/CodeGen/X86/apx/compress-evex.mir
index c0ecfac06aa75..24f7335cc9bde 100644
--- a/llvm/test/CodeGen/X86/apx/compress-evex.mir
+++ b/llvm/test/CodeGen/X86/apx/compress-evex.mir
@@ -139,3 +139,10 @@ body: |
$ax = XOR16rr_ND $ax, killed $di, implicit-def dead $eflags
RET64 $rax
...
+---
+name: setzuccm_2_setccm
+body: |
+ bb.0.entry:
+ ; CHECK: sete 7(%rsp) # EVEX TO LEGACY Compression encoding: [0x0f,0x94,0x44,0x24,0x07]
+ SETZUCCm $rsp, 1, $noreg, 7, $noreg, 4, implicit killed $eflags
+...
diff --git a/llvm/test/TableGen/x86-instr-mapping.inc b/llvm/test/TableGen/x86-instr-mapping.inc
index 6d2873ed4e749..c22dd34ef981c 100644
--- a/llvm/test/TableGen/x86-instr-mapping.inc
+++ b/llvm/test/TableGen/x86-instr-mapping.inc
@@ -158,6 +158,7 @@ static const X86TableEntry X86CompressEVEXTable[] = {
{ X86::SARX32rr_EVEX, X86::SARX32rr },
{ X86::SARX64rm_EVEX, X86::SARX64rm },
{ X86::SARX64rr_EVEX, X86::SARX64rr },
+ { X86::SETZUCCm, X86::SETCCm },
{ X86::SHLX32rm_EVEX, X86::SHLX32rm },
{ X86::SHLX32rr_EVEX, X86::SHLX32rr },
{ X86::SHLX64rm_EVEX, X86::SHLX64rm },
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 9abb1943380f2..3926807170f5b 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -189,13 +189,14 @@ void X86InstrMappingEmitter::emitCompressEVEXTable(
RecognizableInstrBase RI(*Inst);
bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
+ bool IsSETZUCCm = Name == "SETZUCCm";
// Add VEX encoded instructions to one of CompressedInsts vectors according
// to it's opcode.
if (RI.Encoding == X86Local::VEX)
CompressedInsts[RI.Opcode].push_back(Inst);
// Add relevant EVEX encoded instructions to PreCompressionInsts
else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
- (!RI.HasEVEX_B || IsND))
+ (!RI.HasEVEX_B || IsND || IsSETZUCCm))
PreCompressionInsts.push_back(Inst);
}
diff --git a/llvm/utils/TableGen/X86ManualInstrMapping.def b/llvm/utils/TableGen/X86ManualInstrMapping.def
index 662c13eb1b5f5..deff2107e399a 100644
--- a/llvm/utils/TableGen/X86ManualInstrMapping.def
+++ b/llvm/utils/TableGen/X86ManualInstrMapping.def
@@ -333,6 +333,7 @@ ENTRY(VBROADCASTSDZ256rm, VBROADCASTSDYrm)
ENTRY(VBROADCASTSDZ256rr, VBROADCASTSDYrr)
ENTRY(VPBROADCASTQZ256rm, VPBROADCASTQYrm)
ENTRY(VPBROADCASTQZ256rr, VPBROADCASTQYrr)
+ENTRY(SETZUCCm, SETCCm)
#undef ENTRY
#ifndef NOCOMP_ND
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phoebewang
reviewed
Dec 5, 2025
| --- | ||
| name: setzuccm_2_setccm | ||
| body: | | ||
| bb.0.entry: |
phoebewang
reviewed
Dec 5, 2025
| // c. NDD (EVEX) -> non-NDD (legacy) | ||
| // d. NF_ND (EVEX) -> NF (EVEX) | ||
| // e. NonNF (EVEX) -> NF (EVEX) | ||
| // f. SETZUCCm (EVEX) -> SETCCm |
KanRobert
approved these changes
Dec 5, 2025
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/198/builds/10281 Here is the relevant piece of the build log for the reference |
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/72/builds/16592 Here is the relevant piece of the build log for the reference |
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setzucc with memory operand is same as setcc but the later is shorter.