Testing firmware on OFS-XF2GT4

[daniel-dona]

Just compiled and flashed the firmware into this switch 4x2.5G + 2x10G [SFP+] with an RTL8372N:

Some things work, other not yet.

WORKING:

• Copper ports (at least tested up to 1Gb): traffic is managed without any noticeable problem.

NOT WORKING:

• SFP+ port/module: I get a <SFP-RX OK> on the first SFP+ port when inserting the module and <SFP-RX LOS> removing it, but is not detected in any other way.

Running the sfp command I got:

> sfp

Rate: a0  Encoding: a0
����������������������������������������
> 

• LED gpios: some of the copper ports when connected turn other ports LEDs, seems like the first port uses the correct LED, then the second one uses the orange led of the first port and so on.

I can perform additional testing if it can help.

[daniel-dona]

Running sfp with the module inserted on the second port seems to work, or at least detect the module:

> sfp

Rate: 67  Encoding: 06
SFP+ Module     �e10G-SFP-SR-C    02  
>

[logicog]

Thanks for trying this firmware and also reporting the issues!

The device that you use should be possible to support. The 4 + 2 SFP+ port devices are our standard test devices.

From the errors it looks like the GPIOs of the first port do not work properly regarding the I2C needed to read the SFP module information. Without that information, the module is not initialized. The second port seems to work. Looking at the link you sent it also seems like the GPIOs do not work, hence the boot loop (the managed switches usually have a reset button and if this is always on, because the GPIO is not correctly mapped or not there, then this will lead to a boot loop).
So we will need to fix the GPIOs used.

You seem to have CLI access. Could you use thegpio command to see the GPIO configuration when the modules are inserted/removed? It may be possible to deduce the pins used. For this you may need to repeat this test several times since some pins are used for other purposes and constantly change from high to low.
Once we have a basic idea we could further figure this out using regset/regget.

Of course if there are e.g. update images of the switch to download from somewhere, the straightforward approach is to just look into that with a tool such as ghidra.

I also hope @vDorst takes a look at this since he is the GPIO expert.

[daniel-dona]

Reading the GPIO values on a loop I identified a bit for detecting each SPF module.

No modules:

 GPIO_32_63: 0a 7f cb **ff**

SFP module on port 5

 GPIO_32_63: 0a 7f cb **df**

SFP module on port 6

 GPIO_32_63: 0a 7f cb **bf**

With the SFP module inserted, this could be the LOS pin:

SFP module on port 5, signal:

GPIO_00_31: ff fb **3b** ff

SFP module on port 5, no signal:

GPIO_00_31: ff fb **3d** ff

SFP module on port 6, signal:

GPIO_00_31: **fc** fb 3d ff

SFP module on port 6, no signal:

GPIO_00_31: **ff** fb 3d ff

I tried to modify the function handle_sfp to handle this but for now is just detecting the module, with no connectivity.

Also, searching GitHub for other RTL8372 references I found this: https://github.com/JiaY-shi/rtl83xx/tree/main/src/rtl8372, not sure if it could be relevant but is a recent upload.

[daniel-dona]

The original firmware is here: test.bin.zip

[logicog]

I'll look into that.

The source code is known to us since some weeks, it was published also as part of a GPL dump by TP-Link for their TP-Link BE550 device. So it can probably be used under the GPL. One problem is that this does not cover the 8051 part of the SoC.

Could you try also varying the following: There is an sfp read routine, which configures the SDA and SCL pins for the I2C transfer to the SFP EEProm. The relevant bits are described

uint8_t sfp_read_reg(uint8_t slot, uint8_t reg)
{
	if (slot == 0) {
		reg_read_m(RTL837X_REG_I2C_CTRL);
		sfr_mask_data(1, 0xfc, 0x70);  // 0x1c = 011 100 <<<<<
		reg_write_m(RTL837X_REG_I2C_CTRL);
	} else {
		reg_read_m(RTL837X_REG_I2C_CTRL);
		sfr_mask_data(1, 0xfc, 0x6c);  // 0x1b = 011 011 <<<<<<
		reg_write_m(RTL837X_REG_I2C_CTRL);
	}
...

RTL837X_REG_I2C_CTRL is called in the GPL sources:

#define RTL8373_I2C_MST1_CTRL1_ADDR                                                                           (0x418)
  #define RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET                                                             (22)
  #define RTL8373_I2C_MST1_CTRL1_READ_MODE_MASK                                                               (0x1 << RTL8373_I2C_MST1_CTRL1_READ_MODE_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_OFFSET                                                        (20)
  #define RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_MASK                                                          (0x3 << RTL8373_I2C_MST1_CTRL1_MEM_ADDR_WIDTH_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_OFFSET                                                            (16)
  #define RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_MASK                                                              (0xF << RTL8373_I2C_MST1_CTRL1_DATA_WIDTH_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_OFFSET                                                           (13)
  #define RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_MASK                                                             (0x7 << RTL8373_I2C_MST1_CTRL1_SCL_OUT_SEL_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET                                                           (10)
  #define RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK                                                             (0x7 << RTL8373_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET                                                              (3)
  #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_MASK                                                                (0x7F << RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET                                                                  (2)
  #define RTL8373_I2C_MST1_CTRL1_RWOP_MASK                                                                    (0x1 << RTL8373_I2C_MST1_CTRL1_RWOP_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET                                                              (1)
  #define RTL8373_I2C_MST1_CTRL1_I2C_FAIL_MASK                                                                (0x1 << RTL8373_I2C_MST1_CTRL1_I2C_FAIL_OFFSET)
  #define RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET                                                              (0)
  #define RTL8373_I2C_MST1_CTRL1_I2C_TRIG_MASK                                                                (0x1 << RTL8373_I2C_MST1_CTRL1_I2C_TRIG_OFFSET)

So the sfr_mask_data masks the bits 8-15 of this register. Bits 2-4 (of that 2nd byte) configure the SDA pin, bits 5-7 the SCL pin. As usual for such devices, the SCL line is shared by the 2 SFP+ cages. This leaves 6 possibilities for the SDA line (one is already taken by the other cage). Could you try this until you get a result for reading the EEPROM of the SFP-module in both cages?
Note that this is probably not immediately a pin number because the SDA and SCL fields for the second cage have the same values. There are probably a number of physical pins on the SoC that can be addressed by these bits and a value for SDA may signify a different pin than the same value for SCL. There also may be a pin-mux configuring this further, but I was not able to find it in the source code.

[logicog]

After some hours with ghidra, I am quite convinced that the OFS-XF2GT4 has the same SDA/SCL settings for the SFP+ cages as the default device. The relevant code looks identical and does the following:

  if (bVar2 == 0 && bVar3 == 0) { <<<<< Check for cage 1/2
    write_xmem_32(0xb5,0xf);
    write_xmem_32(0xb9,0xd);
    write_xmem_32(0xbd,3);    <<<<<<<<<<<<<<<<< SCL pin
    rtl8373_setAsicRegBits(0x418);
    write_xmem_32(0xb5,0xc);
    write_xmem_32(0xb9,10);
    sda_pin = 3;
  }
  else {
    if (bVar3 == 0) {
      bVar3 = bVar2 ^ 1;
    }
    if (bVar3 != 0) goto LAB_CODE1__cdf0;
    write_xmem_32(0xb5,0xf);
    write_xmem_32(0xb9,0xd);
    write_xmem_32(0xbd,3);  <<<<<<<<<<<<<<<< SCL pin
    rtl8373_setAsicRegBits(0x418);
    write_xmem_32(0xb5,0xc);
    write_xmem_32(0xb9,10);
    sda_pin = 4;
  }
  write_xmem_32(0xbd,(uint)sda_pin);
  rtl8373_setAsicRegBits(0x418); <<<<<<<<<<<<<<< Set the SDA pin

This is identical to the current code. In PR#37 I have made the I2C configuration use less magic numbers.
I am not able to find the GPIOs checked for LOS/Module insert.
There are few options left to explain the issue:

• the GPIOs you use are wrong. Can you verify and then use the sfp command to verify that the right EEPROM of a module in the correct cage is read?
• The SFP cages have switched SerDes connections, i.e. data connection to the SoC. In that case, the GPIOs are all correct and map to the right I2C bus, but the SerDes behind are wrong (you said no connection, right, not: I am not able to read the SFP eeprom). In that case:

There are 2 lines which configure the SerDes (SDS) for a given SFP cage. They are 0 and 1. They could be the wrong way round, i.e. one needs to change 1 to 0 and 0 to 1 in the lines with:
sds_config(1, sfp_rate_to_sds_config(rate));

[daniel-dona]

Hi! I can confirm I2C is working as expected, I thought originally it wasn't because the sfp command was only reading one slot, but with minor changes in the code I was able to read both.

Also, using:

  #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET                                                              (3)
  #define RTL8373_I2C_MST1_CTRL1_DEV_ADDR_MASK                                                                (0x7F << RTL8373_I2C_MST1_CTRL1_DEV_ADDR_OFFSET)

I made some additions to the reading logic to also read the diagnostics of the module (addr 0x51) and seems to work fine too.

// bits [9:8] → upper 2 bits (byte 1, bits [1:0])
// bits [7:3] → lower 5 bits (byte 0, bits [7:3])

if(page == 0){
	dev_addr = 0x50;
	sfr_mask_data(1, 0x03, (dev_addr >> 5) & 0x03);
	sfr_mask_data(0, 0xF8, (dev_addr << 3) & 0xF8);
}else{
	dev_addr = 0x51;
	sfr_mask_data(1, 0x03, (dev_addr >> 5) & 0x03);
	sfr_mask_data(0, 0xF8, (dev_addr << 3) & 0xF8);
}
reg_write_m(RTL837X_REG_I2C_CTRL);

> sfp

============================
## SFP 00 EEPROM Dump
============================
Identifier: 0x03  Encoding: 06  Rate: 67  Wavelength: 850 nm
Vendor: SFP+ Module     
PN: 10G-SFP-SR-C    
SN: 202409050064    

----------------------------
[Diagnostics Data]
Temperature: 37.18 °C 
Voltage: 3348600 µV
TX Bias: 8112 µA
TX Power: 559500 µW
RX Power: 38500 µW
----------------------------

============================
## SFP 01 EEPROM Dump
============================
Identifier: 0x03  Encoding: 06  Rate: 67  Wavelength: 850 nm
Vendor: SFP+ Module     
PN: 10G-SFP-SR-C    
SN: 202409050063    

----------------------------
[Diagnostics Data]
Temperature: 36.50 °C 
Voltage: 3318600 µV
TX Bias: 8200 µA
TX Power: 596200 µW
RX Power: 88700 µW
----------------------------

About the sds_config(1, sfp_rate_to_sds_config(rate)); I tried already flipping the 1 and 0 on both modules without success. Another thing I notice, inserting the module (first SFP port) makes stat report a different port (4?) to be up:

<MODULE REMOVED>

<new link: 0x00000000, was 0x00004000>


> stat

 Port	State	Link	TxGood		TxBad		RxGood		RxBad
4	Off	Down	0x00000000	0x00000000	0x00000000	0x00000000	
5	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
6	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
7	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
8	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	
9	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	

> db

<MODULE INSERTED>  Rate: 67  Encoding: 06

SFP+ Module     �e10G-SFP-SR-C    02  
sds_config sds: 00, mode: 1a

RTL837X_REG_SDS_MODES: 0x0000035a

Trying to set SDS mode to 0x1a

<new link: 0x00004000, was 0x00000000>


> stat

 Port	State	Link	TxGood		TxBad		RxGood		RxBad
4	Off	Up	0x00000000	0x00000000	0x00000000	0x00000000	
5	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
6	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
7	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
8	NO SFP	Up	0x00000000	0x00000000	0x00000000	0x00000000	
9	NO SFP	Up	0x00000000	0x00000000	0x00000000	0x00000000	

> 

Does not happen when inserting the module on the second SFP port:

<MODULE 2 REMOVED>


> stat

 Port	State	Link	TxGood		TxBad		RxGood		RxBad
4	Off	Down	0x00000000	0x00000000	0x00000000	0x00000000	
5	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
6	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
7	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
8	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	
9	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	

> bb

<MODULE 2 INSERTED>  Rate: 67  Encoding: 06
SFP+ Module     �e10G-SFP-SR-C    02  
sds_config sds: 01, mode: 1a

RTL837X_REG_SDS_MODES: 0x0000035a

Trying to set SDS mode to 0x1a


> stat

 Port	State	Link	TxGood		TxBad		RxGood		RxBad
4	Off	Down	0x00000000	0x00000000	0x00000000	0x00000000	
5	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
6	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
7	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
8	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	
9	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	

> 

And I also noticed the message <new link: 0x00004000, was 0x00000000> appears when the the module have connectivity (fiber is inserted, with a working module at the other end). Does that means SerDes is working?

Some of the code changes I have been playing with: daniel-dona@c850663 (I can clean the code and prepare a PR for the SFP diagnostics part if you are interested)

[logicog]

This is amazing stuff you have reading the additional information page of the EEPROM! It would be great to have PR for that. I saw in the source dump you pointed to that it is also possible to read more than 1 byte (up to 15) via I2C. Did you investigate that?

The ports shown on the CLI are the logical ports from the point of the SoC communicating with its internal PHYs (it probably has an RTL8224 inside) and the external ones. The web-pages show the translation to physical ports (grep for log_to_phys_port), this is so to say for end-users...
There are basically 3 geometries:
4 x2.5GBit + 2SFP+ this is the default for the code, uses RTL8372
4x2.5 + 1x2.5GBit (RTL8221) + 1xSFP+, uses RTL8372 + RTL8221B
8x2.5GBit + 1xSFP+, uses RTL8373 + RTL8224

The link change shows the information in a register that according to the source dump has the name RTL8373_MAC_LINK_SPD_STS_ADDR, which shows the link speed of the SerDes to the MAC. For a 10GBit module this should always be an 0x4, which is 10GR for fiber. So one of the links works. The other does not.

There are some more settings to configure the SDS such as polarity. Maybe have a look into the sources to see whether there is something obvious?

If this does not help, I can add tracing to the original image. It would show every register read/write, SDS read/write and PHY read/write on the CLI from the point of view of the 8051 CPU. You have probably seen some comments with such traces in the code. I will have access to my 4+2 device again on Tuesday and can only work on tracing from that time on. With tracing these issues are typically rather easy to fix, but it requires a bit of work to instrument the image...

[logicog]

Can you try to patch your image using the following assembly code:
rwintercept_test.asm
Instructions on how to assemble and use the resulting .hex to patch the test.bin image are in the code. The injector binary is in the tools directory of the Repository code and should be automatically built already. The image will then print traces of all register reads (r), writes (R), PHY reads(p), PHY writes (P), SDS reads (s) and SDS writes (S). In the code for the phy rw intercepts is disabled as it is probably irrelevant in your case and is very chatty. I did however test it (it is very easy to get the addresses wrong), and it seems to work.

A sample trace may then look like this (only register writes, and SDS operations):

�R000c-002a0000 R000c-20206818 R02f8-0000ffff R02f4-0000fffa R02f8-0000ffff R02f4-0000fff0 R6330-00005555 R6330-00005515 R6334-000000f0 R6454-00007000 R65e0-3fffffc0 R65e0-3ffff040 R65e0-3ffc4040 R65e0-3f144040 R65e0-08144040 R65e4-0c3fffc9 R65e4-0c3ff309 R65e4-0c37f309 R65e4-1037f309 R65e8-12450391 R65e8-12454391 R65ec-19616555 R65ec-19616555 R65f0-2079d65a R65f0-1c79d65a R65f4-0002389d R65f4-0002381d R65f4-0002181d R65d8-3ffbedff R6520-0021e5b0 R6520-0021e430 R65f8-0000001b R65fc-33333000 R6600-00000003 R65dc-7fffff00 R65dc-7f249740 R7f8c-30000000 R7f8c-30db68bf R654c-00000040 R654c-00010040 R6548-01740141 R6540-01400145 R6528-00f00000
[Configuration SerDes of RTL8372, also pre-configuration 2Fiber slots]
q000000:1403 Q000000:1603 q010000:1403 Q010000:1603 q000602:0000 Q000602:2000 q010602:0000 Q010602:2000 q000000:1603 Q000000:1603 q010000:1603 Q010000:1603 q000602:2000 Q000602:2000 q010602:2000 Q010602:2000 R7b20-000003ff R7b20-000003fa R7b20-000003fa Q002110:4480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f Q003610:0200 Q002e04:0080 Q002e06:0408 Q002e07:020d Q002e09:0601 Q002e0b:222c Q002e0c:a217 Q002e0d:fe40 Q002e15:f5c1 Q002e16:0443 Q002e1d:abb0 Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100 q001f0b:0003 Q001f0b:000f q002000:0000 Q002000:0030 q002000:0030 Q002000:0010 q002000:0010 Q002000:0050 q002000:0050 Q002000:00d0 q002000:00d0 Q002000:0cd0 q002000:0cd0 Q002000:04d0 q002000:04d0 Q002000:04d0 q002000:04d0 Q002000:0cd0 q002000:0cd0 Q002000:00d0 q002000:00d0 Q002000:00d0 q002000:00d0 Q002000:0050 q002000:0050 Q002000:0010 q002000:0010 Q002000:0010 q002000:0010 Q002000:0030 q002000:0030 Q002000:0000 q001f00:0000 Q001f00:000b q001f00:000b Q001f00:0000 R7b20-000003fa R7b20-0000035a R7b20-0000035a Q012110:4480 Q012113:0400 Q012118:6d02 Q01211b:424e Q01211d:0002 Q01361c:1390 Q013614:003f Q013610:0200 Q012e04:0080 Q012e06:0408 Q012e07:020d Q012e09:0601 Q012e0b:222c Q012e0c:a217 Q012e0d:fe40 Q012e15:f5c1 Q012e16:0443 Q012e1d:abb0 Q010612:5078 Q010706:9401 Q010708:9401 Q01070a:9401 Q01070c:9401 Q011f0b:0003 Q010603:c45c Q01061f:2100 q011f0b:0003 Q011f0b:000f q012000:0000 Q012000:0030 q012000:0030 Q012000:0010 q012000:0010 Q012000:0050 q012000:0050 Q012000:00d0 q012000:00d0 Q012000:0cd0 q012000:0cd0 Q012000:04d0 q012000:04d0 Q012000:04d0 q012000:04d0 Q012000:0cd0 q012000:0cd0 Q012000:00d0 q012000:00d0 Q012000:00d0 q012000:00d0 Q012000:0050 q012000:0050 Q012000:0010 q012000:0010 Q012000:0010 q012000:0010 Q012000:0030 q012000:0030 Q012000:0000 q011f00:0000 Q011f00:000b q011f00:000b Q011f00:0000 q012100:4902 Q012100:4906 q013605:0000 Q013605:4000 Q011f02:001f q011f15:0077 q010500:100d q010500:100d q002100:4902 Q002100:4906 q003605:0000 Q003605:4000 Q001f02:001f q001f15:0096 R0a90-000000fc R0a94-0000596a R5fd4-001a914a R1538-00000e37 R1538-00000e37 R1538-00000f37 R1638-00000e37 R1638-00000e37 R1638-00000f37 R1738-00000e37 R1738-00000e37 R1738-00000f37 R1838-00000e37 R1838-00000e37 R1838-00000f37 R1938-00000e37 R1938-00000e37 R1938-00000f37 R1a38-00000e37 R1a38-00000e37 R1a38-00000f37 R0b7c-000000f8 R7124-00001050 R7128-00001050 R712c-00001050 R7130-00001050 R7134-00001050 R7138-00001050 R713c-00001050 R7140-00001050 R7144-00001050 R7148-00001050 R6040-00000031
LINE 1478, RL6818C_pwr_on_patch_phy_v007 , patch 0xf0 finished!
R632c-001f8540 
RTL8371B start
R0414-00000000 R0414-00000000 R0414-00000000 R0414-00000000 R0414-00000000
R0418-00100280 R0418-00100280 R0418-00100280 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R7f90-40000001 R7f90-40000041 R06f4-00000001
R0418-00106280 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000c R0418-00106e81 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000b R0418-00106e81 R7b20-0000035a R7b20-00000344 R7b20-00000344
SERDES_SGMII/fiber1g 108,LINE 2000
[SerDes Configuration fiber SFP]
Q002110:6480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f Q003610:0300 Q002404:0080 Q002407:1201 Q002409:0601 Q00240b:232c Q00240c:9217 Q00240f:5b50 Q002415:e7c1 Q002416:0443 Q00241d:abb0 Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100 q001f05:3ff0 Q001f05:3ff4 q001f05:3ff4 Q001f05:3ff4 q000204:0020 Q000204:01a0 q000002:70d0 Q000002:73d0 q000004:0749 Q000004:074d q002000:0000 Q002000:0030 q002000:0030 Q002000:0010 q002000:0010 Q002000:0050 q002000:0050 Q002000:00d0 q002000:00d0 Q002000:0cd0 q002000:0cd0 Q002000:04d0 q002000:04d0 Q002000:04d0 q002000:04d0 Q002000:0cd0 q002000:0cd0 Q002000:00d0 q002000:00d0 Q002000:00d0 q002000:00d0 Q002000:0050 q002000:0050 Q002000:0010 q002000:0010 Q002000:0010 q002000:0010 Q002000:0030 q002000:0030 Q002000:0000 q001f00:0000 Q001f00:000b q001f00:000b Q001f00:0000
[Starts polling GPIOs:]
R0418-00106e80 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0420-0000000c R0418-00107281 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0420-0000000b R0418-00107281 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d q00011d:8000 R06f4-00000002 R0418-00107280
R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000c R0418-00106e81 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000b R0418-00106e81 R0418-00106e80 R0418-00107280 R0418-00107280

And now the polling part with switched on Register-Reads:

RTL8371B:
r06f4:0000001c R06f4-0000001d [the second counter is incremented once per second]
r0048:0a7bdb9b [GPIO read for identifying SFP insert/removal, and RX-LOS]
r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 [I2C transfer for SFP EEProm]
r7b20:00000344 [checks SerDes modes on MAC side]
r0048:0a7bdb9b [GPIO read REPEATS the above]
r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006
r7b20:00000344 r7b20:00000344 [checks SDS mode, twice seems better]
q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0057 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 [Writes stuff to SDS settings]
r06f4:0000001d R06f4-0000001e [the next second]
r0048:0a7bdb9b [Read GPIO]
r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9f r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006 r7b20:00000344 r7b20:00000344 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 r06f4:0000001e R06f4-0000001f r0048:0a7bdb9f r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9f r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006 r7b20:00000344 r7b20:00000344 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 r06f4:0000001f R06f4-00000020 r0048:0a7bdb9b r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9b r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 

The image did of course not really work for me as the GPIOs for the second SFP are all wrong. My guess is that there are differences for your device in the way the second SerDes is configured, which is the reason that there is no link. Also check the MAC settings. You can probably ignore the PHY completely.

[daniel-dona]

Can you try to patch your image using the following assembly code: rwintercept_test.asm Instructions on how to assemble and use the resulting .hex to patch the test.bin image are in the code. The injector binary is in the tools directory of the Repository code and should be automatically built already. The image will then print traces of all register reads (r), writes (R), PHY reads(p), PHY writes (P), SDS reads (s) and SDS writes (S). In the code for the phy rw intercepts is disabled as it is probably irrelevant in your case and is very chatty. I did however test it (it is very easy to get the addresses wrong), and it seems to work.

A sample trace may then look like this (only register writes, and SDS operations):

�R000c-002a0000 R000c-20206818 R02f8-0000ffff R02f4-0000fffa R02f8-0000ffff R02f4-0000fff0 R6330-00005555 R6330-00005515 R6334-000000f0 R6454-00007000 R65e0-3fffffc0 R65e0-3ffff040 R65e0-3ffc4040 R65e0-3f144040 R65e0-08144040 R65e4-0c3fffc9 R65e4-0c3ff309 R65e4-0c37f309 R65e4-1037f309 R65e8-12450391 R65e8-12454391 R65ec-19616555 R65ec-19616555 R65f0-2079d65a R65f0-1c79d65a R65f4-0002389d R65f4-0002381d R65f4-0002181d R65d8-3ffbedff R6520-0021e5b0 R6520-0021e430 R65f8-0000001b R65fc-33333000 R6600-00000003 R65dc-7fffff00 R65dc-7f249740 R7f8c-30000000 R7f8c-30db68bf R654c-00000040 R654c-00010040 R6548-01740141 R6540-01400145 R6528-00f00000
[Configuration SerDes of RTL8372, also pre-configuration 2Fiber slots]
q000000:1403 Q000000:1603 q010000:1403 Q010000:1603 q000602:0000 Q000602:2000 q010602:0000 Q010602:2000 q000000:1603 Q000000:1603 q010000:1603 Q010000:1603 q000602:2000 Q000602:2000 q010602:2000 Q010602:2000 R7b20-000003ff R7b20-000003fa R7b20-000003fa Q002110:4480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f Q003610:0200 Q002e04:0080 Q002e06:0408 Q002e07:020d Q002e09:0601 Q002e0b:222c Q002e0c:a217 Q002e0d:fe40 Q002e15:f5c1 Q002e16:0443 Q002e1d:abb0 Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100 q001f0b:0003 Q001f0b:000f q002000:0000 Q002000:0030 q002000:0030 Q002000:0010 q002000:0010 Q002000:0050 q002000:0050 Q002000:00d0 q002000:00d0 Q002000:0cd0 q002000:0cd0 Q002000:04d0 q002000:04d0 Q002000:04d0 q002000:04d0 Q002000:0cd0 q002000:0cd0 Q002000:00d0 q002000:00d0 Q002000:00d0 q002000:00d0 Q002000:0050 q002000:0050 Q002000:0010 q002000:0010 Q002000:0010 q002000:0010 Q002000:0030 q002000:0030 Q002000:0000 q001f00:0000 Q001f00:000b q001f00:000b Q001f00:0000 R7b20-000003fa R7b20-0000035a R7b20-0000035a Q012110:4480 Q012113:0400 Q012118:6d02 Q01211b:424e Q01211d:0002 Q01361c:1390 Q013614:003f Q013610:0200 Q012e04:0080 Q012e06:0408 Q012e07:020d Q012e09:0601 Q012e0b:222c Q012e0c:a217 Q012e0d:fe40 Q012e15:f5c1 Q012e16:0443 Q012e1d:abb0 Q010612:5078 Q010706:9401 Q010708:9401 Q01070a:9401 Q01070c:9401 Q011f0b:0003 Q010603:c45c Q01061f:2100 q011f0b:0003 Q011f0b:000f q012000:0000 Q012000:0030 q012000:0030 Q012000:0010 q012000:0010 Q012000:0050 q012000:0050 Q012000:00d0 q012000:00d0 Q012000:0cd0 q012000:0cd0 Q012000:04d0 q012000:04d0 Q012000:04d0 q012000:04d0 Q012000:0cd0 q012000:0cd0 Q012000:00d0 q012000:00d0 Q012000:00d0 q012000:00d0 Q012000:0050 q012000:0050 Q012000:0010 q012000:0010 Q012000:0010 q012000:0010 Q012000:0030 q012000:0030 Q012000:0000 q011f00:0000 Q011f00:000b q011f00:000b Q011f00:0000 q012100:4902 Q012100:4906 q013605:0000 Q013605:4000 Q011f02:001f q011f15:0077 q010500:100d q010500:100d q002100:4902 Q002100:4906 q003605:0000 Q003605:4000 Q001f02:001f q001f15:0096 R0a90-000000fc R0a94-0000596a R5fd4-001a914a R1538-00000e37 R1538-00000e37 R1538-00000f37 R1638-00000e37 R1638-00000e37 R1638-00000f37 R1738-00000e37 R1738-00000e37 R1738-00000f37 R1838-00000e37 R1838-00000e37 R1838-00000f37 R1938-00000e37 R1938-00000e37 R1938-00000f37 R1a38-00000e37 R1a38-00000e37 R1a38-00000f37 R0b7c-000000f8 R7124-00001050 R7128-00001050 R712c-00001050 R7130-00001050 R7134-00001050 R7138-00001050 R713c-00001050 R7140-00001050 R7144-00001050 R7148-00001050 R6040-00000031
LINE 1478, RL6818C_pwr_on_patch_phy_v007 , patch 0xf0 finished!
R632c-001f8540 
RTL8371B start
R0414-00000000 R0414-00000000 R0414-00000000 R0414-00000000 R0414-00000000
R0418-00100280 R0418-00100280 R0418-00100280 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R041c-00000000 R7f90-40000001 R7f90-40000041 R06f4-00000001
R0418-00106280 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000c R0418-00106e81 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000b R0418-00106e81 R7b20-0000035a R7b20-00000344 R7b20-00000344
SERDES_SGMII/fiber1g 108,LINE 2000
[SerDes Configuration fiber SFP]
Q002110:6480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f Q003610:0300 Q002404:0080 Q002407:1201 Q002409:0601 Q00240b:232c Q00240c:9217 Q00240f:5b50 Q002415:e7c1 Q002416:0443 Q00241d:abb0 Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100 q001f05:3ff0 Q001f05:3ff4 q001f05:3ff4 Q001f05:3ff4 q000204:0020 Q000204:01a0 q000002:70d0 Q000002:73d0 q000004:0749 Q000004:074d q002000:0000 Q002000:0030 q002000:0030 Q002000:0010 q002000:0010 Q002000:0050 q002000:0050 Q002000:00d0 q002000:00d0 Q002000:0cd0 q002000:0cd0 Q002000:04d0 q002000:04d0 Q002000:04d0 q002000:04d0 Q002000:0cd0 q002000:0cd0 Q002000:00d0 q002000:00d0 Q002000:00d0 q002000:00d0 Q002000:0050 q002000:0050 Q002000:0010 q002000:0010 Q002000:0010 q002000:0010 Q002000:0030 q002000:0030 Q002000:0000 q001f00:0000 Q001f00:000b q001f00:000b Q001f00:0000
[Starts polling GPIOs:]
R0418-00106e80 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0420-0000000c R0418-00107281 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0418-00107280 R0420-0000000b R0418-00107281 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d q00011d:8000 R06f4-00000002 R0418-00107280
R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000c R0418-00106e81 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0418-00106e80 R0420-0000000b R0418-00106e81 R0418-00106e80 R0418-00107280 R0418-00107280

And now the polling part with switched on Register-Reads:

RTL8371B:
r06f4:0000001c R06f4-0000001d [the second counter is incremented once per second]
r0048:0a7bdb9b [GPIO read for identifying SFP insert/removal, and RX-LOS]
r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 [I2C transfer for SFP EEProm]
r7b20:00000344 [checks SerDes modes on MAC side]
r0048:0a7bdb9b [GPIO read REPEATS the above]
r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006
r7b20:00000344 r7b20:00000344 [checks SDS mode, twice seems better]
q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0057 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 [Writes stuff to SDS settings]
r06f4:0000001d R06f4-0000001e [the next second]
r0048:0a7bdb9b [Read GPIO]
r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9f r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006 r7b20:00000344 r7b20:00000344 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 r06f4:0000001e R06f4-0000001f r0048:0a7bdb9f r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9f r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000b r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000006 r7b20:00000344 r7b20:00000344 q012100:4906 Q012100:4906 q013605:4000 Q013605:4000 Q011f02:001f q011f15:0067 q010500:100d q010500:100d r7b20:00000344 q00011d:8000 r06f4:0000001f R06f4-00000020 r0048:0a7bdb9b r0418:00107280 R0418-00107280 r0418:00107280 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000c r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:0000000d r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00106e80 R0420-0000000b r0418:00106e80 R0418-00106e81 r0418:00106e80 r0418:00106e80 r0424:00000001 r7b20:00000344 r0048:0a7bdb9b r0418:00106e80 R0418-00106e80 r0418:00106e80 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 R0420-0000000c r0418:00107280 R0418-00107281 r0418:00107280 r0418:00107280 r0424:00000067 r0418:00107280 R0418-00107280 r0418:00107280 R0418-00107280 r0418:00107280 

The image did of course not really work for me as the GPIOs for the second SFP are all wrong. My guess is that there are differences for your device in the way the second SerDes is configured, which is the reason that there is no link. Also check the MAC settings. You can probably ignore the PHY completely.

I'll test this as soon as I have the hardware in hand next week, thanks!

[daniel-dona]

The boot log with the patched firmware:

rwintercept.zip

(Haven't had time to check the log yet)

[logicog]

Thanks for that! I already see differences in the LED configuration. This should explain the problems with the wrong copper port LEDs blinking. I will send a new led configuration routine later. I would like to understand what the differences mean. Regarding the 2nd cage not working. Could you try PR #39 ? That stands a good chance of fixing the issue.

[logicog]

Could you try the following LED configuration?

void led_config_ofs_xf2gt4(void)
{
	// RTL8373_LED_GLB_ACTIVE
	// r65d8:3ffb6dff R65d8-3ffb6dff
	REG_SET(0x65d8, 0x3ffb6dff);

	// LED initialization
	// r6520:0021fdb0 R6520-0021e5b0 r6520:0021e5b0 R6520-0021e430
	reg_read_m(RTL837X_REG_LED_MODE);
	sfr_mask_data(2, 0xe0, 0x23); 	// Mask blink rate field (0xe0), set blink rate and LED to solid (set bit 1 = bit 17 overall)
	// Configure led-mode (serial?)
	sfr_data[2] = 0xe4;
	sfr_data[3] = 0x30;
	reg_write_m(RTL837X_REG_LED_MODE);

	// Set RLDP blink rate register RTL8373_LED_RLDP_CTRL_1
	// r65f8:00000018 R65f8-0000001b
	REG_SET(0x65f8, 0x0000001b);

	// Set the RLDP mode for copper ports p3-p7 in RTL8373_LED_RLDP_CTRL_2
	// r65fc:00000000 R65fc-33333000 
	REG_SET(0x65fc, 0x33333000);
	// RLDP for port p8 RTL8373_LED_RLDP_CTRL_3
	// r6600:00000000 R6600-00000003 
	REG_SET(0x6600, 0x03);

	// Enable/disable LED GPIOs 0-29: RTL8373_LED_GLB_IO_EN and set LED-PAD-IO via bit 30
	// r65dc:5fffff00 R65dc-7fffff00 r65dc:7fffff00 R65dc-7f249740
	REG_SET(0x65dc, 0x7f249740);

	// Configure PIN MUX
	REG_SET(RTL837X_PIN_MUX_0, 0x30db68bf);

	// Configure LED_SET_0 and set 1, ledid 0/1: RTL8373_LED1_0_SET0, RTL8373_LED1_0_SET1
	// R6548-01740141 R6540-01400145
	REG_SET(0x6548, 0x01740141);
	REG_SET(0x6540, 0x01400145);

	// Configure RTL8373_LED_PORT_SET_SEL
	// r654c:00000000 R654c-00000040 r654c:00000040 R654c-00010040
	REG_SET(0x654c, 0x00010040);

	// There are no ledids 2/3, i.e. RTL8373_LED3_2_SET0, 0x6544 stays unset

	// Further configure LED_SET_1 RTL8373_LED3_0_SET1_0_CTRL1_ADDR
	// r6528:00000000 R6528-00f00000
	REG_SET(0x6528, 0x00f00000);
}

instead of config_led() ? It looks like the LED topology is different. As you can see, the register writes are all directly pulled from the log-file you sent, the relevant parts have been added as comments.

[daniel-dona]

Thanks for that! I already see differences in the LED configuration. This should explain the problems with the wrong copper port LEDs blinking. I will send a new led configuration routine later. I would like to understand what the differences mean. Regarding the 2nd cage not working. Could you try PR #39 ? That stands a good chance of fixing the issue.

Just flashed the PR and no luck with SFP slots, here you have the output of stat with both SFP modules inserted:

> stat

 Port	State	Link	TxGood		TxBad		RxGood		RxBad
5	NO SFP	Down	0x00000000	0x00000000B��0000000	0x00000000	
1	On	Down	0x0000000e	��0000000	0x00000000	0x00000000	
2	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
3	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
4	On	Down	0x00000000	0x00000000	0x00000000	0x00000000	
6	NO SFP	Down	0x00000000	0x00000000	0x00000000	0x00000000	C�
>

BTW, I see some corruption on serial communication using 115200 as baudrate, but works fine if I configure the firmware to use slower ones. Maybe 57600 or 9600 is a better default?

I'll try the changes on LED config next.

[logicog]

It looks like you have different GPIOs for the 2 cages. The issue was before that the 2nd cage was not properly supported at all by the code. The PR was not adapted to your specific setup, but I believe that you already figured out the proper GPIOs earlier for detecting module presence. Once those are used, the PR should properly detect both SFPs and read the EEProm correctly. At least that is what I hope. Could you try that? If that fails I can also try to identify the correct pins in the image, but that is really work I would like to avoid.

We will need to have per-device defines for the different GPIOs used. Maybe you have an idea how this could be done?

Regarding the 115200 baud, are you sure it is not your cabling and in particular the soldered UART pins? In the past I have had several times issues with the soldering connection to the GND pin: since the ground plane is so large that solder connection often ended up being too cold and thus fragile so that after some time it started to create similar problems as you see. If this is not the case, we can define this per-device. It is already a #define in rtlplayground.c. 115200 is used as a default because it is so popular with embedded devices. I did tests in the past with the same cabling and very cheap FT232 UART-USB converter I currently use (but other devices) and 576000baud was never a problem.