Verilator width resolution

marnovandermaas · marnovandermaas · commit 515481d29a4b · 2025-01-23T11:50:35.000Z
diff --git a/rtl/cheri_ex.sv b/rtl/cheri_ex.sv
@@ -307,7 +307,7 @@ module cheri_ex import cheri_pkg::*; #(
     unique case (1'b1)
       cheri_operator_i[CGET_PERM]:
         begin
-          result_data_o       = {19'h0, rf_fullcap_a.perms};
+          result_data_o       = {20'h0, rf_fullcap_a.perms};
           result_cap_o        = NULL_REG_CAP;   // zerout the cap msw
           cheri_rf_we_raw     = 1'b1;
           cheri_ex_valid_raw  = 1'b1;
diff --git a/rtl/cheri_trvk_stage.sv b/rtl/cheri_trvk_stage.sv
@@ -57,7 +57,7 @@ module cheri_trvk_stage #(
   logic  [2:1] range_ok_q;
 
 
-  assign base32    = get_bound33(in_cap_q.base, {2{in_cap_q.base_cor}}, in_cap_q.exp, in_data_q);
+  assign base32    = 32'(get_bound33(in_cap_q.base, {2{in_cap_q.base_cor}}, in_cap_q.exp, in_data_q));
   assign tsmap_ptr = (base32 - HeapBase) >> 3;
 
   /* verilator lint_off WIDTH */
