Update hm2_bspi_setup_chan parameters

docs/man/man3/hm2_bspi_setup_chan.asciidoc

@@ -6,7 +6,7 @@
 
 :manmanual: HAL Components
 :mansource: ../man/man3/hm2_bspi_setup_chan.asciidoc
-:man version : 
+:man version :
 
 
 == NAME
@@ -17,52 +17,53 @@
 
 == SYNTAX
 **int hm2_bspi_setup_chan** ( **char** *__name__, **int** __chan__, **int** __cs__, **int** __bits__, **float** __mhz__,
-**int** __delay__, **int** __cpol__, **int** __cpha__, **int** __clear__, **int** __echo__ )
+**int** __delay__, **int** __cpol__, **int** __cpha__, **int** __noclear__, **int** __noecho__, **int** __samplelate__  )
 
 
 
 == DESCRIPTION
-**hm2_bspi_setup_chan** Setup the bspi channel "chan" on the bspi instance 
-"name". 
+**hm2_bspi_setup_chan** Setup the bspi channel "chan" on the bspi instance
+"name".
 
-"name" is a unique string given to each bspi channel during hostmot2 
+"name" is a unique string given to each bspi channel during hostmot2
 setup. +
 The names of the available
-channels are printed to standard output during the driver loading process and 
+channels are printed to standard output during the driver loading process and
 take the form: +
 **hm2_**__<board name>.<board index>__.**bspi**.__<index>__ +
 For example +
 **hm2_5i23.0.bspi.0** +
 
 Channels are numbered 0 to 15. +
 The value on the chip-select lines is set by cs and need not match the
-channel number. 
-BSPI supports 4 chip select lines, so the valid range for cs is 
-0-15. 
+channel number.
+BSPI supports 4 chip select lines, so the valid range for cs is
+0-15.
 
 "bits" sets the bit-length of the SPI packet. +
 The maximum supported length
-is 64 bits but this will span two read FIFO entries and will need special 
-handling. 
+is 64 bits but this will span two read FIFO entries and will need special
+handling.
 
-"mhz" sets the chip communication rate. The maximum value for this is 
-half the FPGA base frequency, so for example with a 48MHz 5i23 the max SPI 
+"mhz" sets the chip communication rate. The maximum value for this is
+half the FPGA base frequency, so for example with a 48MHz 5i23 the max SPI
 frequency is 24Mhz. +
-Values in excess of the max supported will be silently 
-rounded down. 
+Values in excess of the max supported will be silently
+rounded down.
 
-"delay" sets the chip select valid delay (in nS). 
+"delay" sets the chip select valid delay (in nS).
 
-"cpha" is the 
-clock phase and "cpol" is the clock polarity (from the device datasheet). 
+"cpha" is the
+clock phase and "cpol" is the clock polarity (from the device datasheet).
 
-"clear" controls whether the frame clear bit is set after the 32 bit buffer 
+"noclear" controls whether the frame clear bit is set after the 32 bit buffer
 transfer. +
-This parameter should be set to 1 when the frame length is greater 
-than 32 bits and the next data in the FIFO contains the other bits. 
+This parameter should be set to 1 when the frame length is greater
+than 32 bits and the next data in the FIFO contains the other bits.
 
-"echo" is sense-inverted, it should be set to 1 for devices which do not return data (such
- as DACs). 
+"noecho" should be set to 1 for devices which do not return data (such as DACs).
+
+"samplelate" left shifts the incomming spi read data, by 1 bit, when set to 1.
 
 
 
@@ -78,7 +79,7 @@ Andy Pugh
 == SEE ALSO
 **hm2_bspi_setup_chan** +
 **hm2_bspi_write_chan** +
-**hm2_tram_add_bspi_frame** + 
-**hm2_allocate_bspi_tram** 
+**hm2_tram_add_bspi_frame** +
+**hm2_allocate_bspi_tram**
 
-See link:https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/mesa_7i65.comp[mesa_7i65.comp] for an example usage
+See link:https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/mesa_7i65.comp[mesa_7i65.comp] for an example usage