This repository contains details of design and working of a 4-bit PISO(Parallel In Serial Out) Shift Register
The shift register which uses parallel input and generates serial output is known as the parallel input serial output shift register or PISO shift register. In this shift register, the input data enters a parallel way and comes out serially. The flip-flops are connected such that the input of the second flip flop is the output of the first flip flop. Since a 4-bit PISO shift register is being implemented , 4 flip flops are used.
PISO Shift Registers are commonly used in
- Communication lines where a number of data lines are multiplexed into single serial data line
- Reading data into a microprocessor
- Transmitter section in Analog to Digital converters
The 4- bit PISO shift register circuit diagram is shown below. This circuit mainly includes 4, D flip flops which are connected as per the diagram shown. The CLK(clock) input signal is connected directly to all the flip flops however the input data is individually connected to every flip flop. Hence it is a synchronous sequential circuit. The previous flip flop’s output, as well as parallel input data, is simply connected to the input of the second flip flop.
In the PISO shift register circuit, the input data is applied to the input pins of the shift registers from D0 to D3 at the same time. On every subsequent clock pulse, output is read from the shift register serially 1-bit at a time from input. Here, one CLK pulse is enough to load the 4-bits of data but four pulses are required to unload all the four bits serially.
In this PISO shift register circuit, logic gates are used. One control signal (Shift/Load) is used to control the parallel input and serial output for selection of loading or shifting function.
For loading, ‘0’ must be given as input to the select line and for shifting, ‘1’ has to given as select input. Hence, a NOT gate is used for the select lines to distinguish loading and shifting functions.
The connections are made as follows
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The NOT gate outputs are connected to inputs of AND gates ‘A2’, ‘A4’, and ‘A6’, and the other inputs of A2, A4 & A6 are the actual data inputs Q, R & S. Here, input ‘P’ is directly connected to D0 input of the first flip flop.
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For AND gates, A1, A3 and A5, one of the inputs is the Shift/Load select line and the other input is connected to the outputs Q0, Q1 and Q2 of respective flip flops.
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The outputs of AND gates A1 and A2 are connected to OR gate O1, the outputs of AND gates A2 and A4 are connected to OR gate O2, The outputs of AND gates A5 and A6 are connected to OR gate O3. -The outputs of OR gates O1, O2 and O3 are connected to inputs of Q1, Q2 and Q3 respectively. The AND gates and OR gates, together, perform the function of a multiplexer. -All the flip flops are to be connected in a single CLK pulse and the flip flops outputs will be in the serial data output. The serial output is taken at the output Q3 of flipflop D3.
Refer to the truth table below to understand the progress after each clock pulse. In the below truth table, input is taken as '1011'. Observe 'Q3' at each clock cycle for the serial output.
Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the "vvp" command. For synthesis, the compiler generates netlists in the desired format.
GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
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For Ubuntu
Open the terminal and enter the following commands$ sudo apt-get update $ sudo apt-get install iverilog $ sudo apt-get install gtkwave
Follow the steps from the below git repository to install yosys on Ubuntu.
https://github.com/YosysHQ/yosys/blob/master/README.md#installation
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
Follow the steps from the below git repository to install OpenLane on Ubuntu.
<a href="https://github.com/The-OpenROAD-Project/OpenLane>https://github.com/The-OpenROAD-Project/OpenLane
Enter below commands
$ sudo apt-get update
$ sudo apt-get install csh
$ sudo apt-get install x11
$ sudo apt-get install xorg
$ sudo apt-get install xorg openbox
$ sudo apt-get install freeglut3-dev
$ sudo apt-get install tcl-dev tk-dev
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic
$ ./configure
$ make
$ sudo make install
To install git, clone this repository and download the required files for simulation, enter the below commands in the terminal.
$ sudo apt install -y git
$ git clone https://github.com/mahati-basavaraju/iiitb_piso
$ cd iiitb_piso
$ iverilog -o iiitb_piso iiitb_piso_tb.v iiitb_piso.v
$ vvp iiitb_piso
$ gtkwave iiitb_piso.vcd
Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.
Synthesis takes place in multiple steps:
- Converting RTL into simple logic gates.
- Mapping those gates to actual technology-dependent logic gates available in the technology libraries.
- Optimizing the mapped netlist keeping the constraints set by the designer intact
Invoke ''yosys' and execute the below commands to perform the synthesis of the above circuit.
$ read_liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ read_verilog iiitb_piso.v
$ synth -top iiitb_piso
$ dfflibmap -liberty ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ abc -liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ show
$ stat
GLS implies running the testbench with netlist as the design under test. It is used to verify the logical correctness of the design after synthesis. It also ensures that the timing constraints are met.
Execute below commands in the project directory to perform GLS.
$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#0 ./verilog_model/primitives.v ./verilog_model/sky130_fd_sc_hd.v
$ ./a.out
$ gtkwave iiitb_piso.vcd
Find below simulation results when a 4-bit input '1011' is provided. Note that data_in is the input data, data_out is the output register, q is a temporary register to indicate shifting and, clk and load are clock and shift/load signals respectively.
Once we complete above steps, we can proceed with the physical design steps.
For this, we use OpenLane flow.
Create a new directory with the project names in OpenLane/designs. This contain a config.json file, a folder names runs and a folder named src. Add the verilog top module file in src folder and edit the config file as below.
The config file should include paths of sky130 .lib files and the vsd_inv .lef file for merging the sky130_vsdnv cells with our design. For detailed steps, visit https://github.com/Devipriya1921/Physical_Design_Using_OpenLANE_Sky130#inverter-standard-cell-layout--spice-extraction
Follow below commands to move to OpenLane working directory and move to OpenLane base.
$ cd OpenLane
$ make mount
To start the OpenLane flow in an interactive mode and to prepare the design, enter below commands.
% ./flow.tcl -interactive
% package require openlane
% prep -design iiitb_piso
To merge the vsd_inv lef file into our design, use below commands.
% set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
% add_lefs -src $lefs
### Synthesis
Next step is to synthesise. Run below command.
% run_synthesis
The statistics after synthesis can be found in the <current_run_directory>/reports/synthesis/1-synthesis.AREA_0.stat.rpt
Flop Ratio
Flop Ratio= No. of d ffs/ No. of cells = 4/13 = 0.3077
(Refer below image)
Find below screenshot of vsd_inv cells in the iiitb_piso.v file under the <current_run_dir>/results/synthesis ( where we can observe all the cell info)
Run floorplan
% run_floorplan
View the floorplan, using the below magic command in the terminal opened in the directory: <current_run_directory>/results/floorplan
$ magic -T /home/mahati/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.min.lef def read iiitb_piso.def &
Refer below image for full view of floorplan
Refer below image for zoomed view of floorplan
Refer below image for the cells on floorplan (one can find them by zooming into the left bottom corner)
The die area and the core area report can be found in <current_run_dir>/reports/floorplan saves as 3-initial_fp_die_area.rpt and 3-initial_fp_core_area.rpt respectively. Find below screenshots.
- Die Area
- Core Area
Run placement
% run_placement
View the placement in the layout, using the below magic command in the terminal opened in the directory: <current_run_directory>/results/placement
$ magic -T /home/mahati/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_piso.def &
Refer below image for full view of layout after placement
Refer below image for zoomed view of layout after placement
The zoomed in view of one of the sky130_inv cell is as below.
Run cts
% run_cts
Run routing
% run_routing
View the layout after routing, using the below magic command in the terminal opened in the directory: <current_run_directory>/results/routing
$ magic -T /home/mahati/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_piso.def &
Refer below image for full view of layout after routing
Refer below image for zoomed view of after routing
One of the sky130_vsdinv instance(Cell 11) can be spotted here
The zoomed in view of one of the sky130_inv cell is as below.
Area
Power Report
Run the entire flow using
./flow.tcl -design iiitb_piso
Install opensta using
sudo apt install opensta
Run the below commands on sta base to get the report_checks
read_liberty -max /home/mahati/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib
read_liberty -min /home/mahati/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib
read_verilog /home/mahati/OpenLane/designs/iiitb_piso_1/runs/RUN_2022.09.27_12.29.44/results/routing/iiitb_piso.resized.v
link_design iiitb_piso
read_sdc /home/mahati/OpenLane/designs/iiitb_piso_1/runs/RUN_2022.09.27_12.29.44/results/cts/iiitb_piso.sdc
read_spef /home/mahati/OpenLane/designs/iiitb_piso_1/runs/RUN_2022.09.27_12.29.44/results/cts/iiitb_piso.nom.spef
set_propagated_clock [all_clocks]
report_checks
report_clock_properties
Max positive slack
Frequency = 1/ (Clock period-Slack) = 1/(65-51.18) = 72.36 MHz
- Mahati Basavaraju
- Kunal Ghosh
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Mahati Basavaraju, Master of Science by Research Student, International Institute of Information Technology, Bangalore mahati.basavaraju@iiitb.ac.in
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
- https://www.elprocus.com/piso-shift-register/
- https://www.electronics-tutorial.net/sequential-logic-circuits/parallel-in-to-serial-out-piso-shift-register/
- https://www.electronicshub.org/shift-registers/
- https://www.youtube.com/watch?v=JzXGiVig4zE
- http://www.vlsifacts.com/synthesis-in-vlsi/
- https://github.com/The-OpenROAD-Project/OpenLane
- https://github.com/Devipriya1921/Physical_Design_Using_OpenLANE_Sky130
- https://github.com/DantuNandiniDevi/iiitb_freqdiv
- https://github.com/Bandaanusha/iiitb_rtc