Simple-RISC-Machine

Simple-RISC-Machine Verilog Project CPEN 211 UBC This was done in a month as part of labs 5-8. This is synthesizable on DE1-soc.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
alu.v		alu.v
alu_tb.v		alu_tb.v
cpu.v		cpu.v
cpu_tb.v		cpu_tb.v
datapath.v		datapath.v
datapath_tb.v		datapath_tb.v
lab8_stage2_tb.v		lab8_stage2_tb.v
lab8_top.v		lab8_top.v
lab8_top_tb.v		lab8_top_tb.v
regfile.v		regfile.v
regfile_tb.v		regfile_tb.v
shifter.v		shifter.v
shifter_tb.v		shifter_tb.v

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