A SPI master component that can be easily integrated in FuseSoC projects. For right now, this repository is being used as a testing ground for some of the BFMs I developed and to help me test the limits of FuseSoC. If you would like the repository that links to my library of FuseSoC components, please click here.
This core currently only has two parameters:
Clock Polarity: The polarity of the clock when the master is not transmitting.
Clock Phase: The phase at which data is being transmitted by the master.
In order to use this core as it is intended, FuseSoC is required to be installed.
Running the simulation:
fusesoc --cores-root . run --target sim midimaster21b:comm:spi-master:0.1.1
Running the simulation with parameters:
fusesoc --cores-root . run --target sim midimaster21b:comm:spi-master:0.1.1 --CLOCK_POLARITY_G 0 --CLOCK_PHASE_G 1