Parallel to UART adapter

This contains the Verilog code to implement a parallel to UART adapter. Additionally, there is a Logisim Evolution project which simulates the circuit implemented in the Verilog code.

Using the code

The only requirement to use the Verilog code is the synthesis tool needs to support the $clog2 instruction.

To open the Logisim Evolution project, Logisim Evolution is required.