Updlibmetal1

boards/nordic/nrf52840dk/board.cmake

@@ -1,5 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
+if(CONFIG_SOC_NRF52840_QIAA)
+  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/support/nrf52840dk_qspi_nrfutil_config.json")
+endif()
+
 board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000")
 board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)

boards/nordic/nrf52840dk/support/nrf52840dk_qspi_nrfutil_config.json

@@ -0,0 +1,22 @@
+{
+  "firmware_config": {
+    "peripheral": "QSPI"
+  },
+  "pins": {
+    "sck": 19,
+    "csn": 17,
+    "io0": 20,
+    "io1": 21,
+    "io2": 22,
+    "io3": 23
+  },
+  "flash_size": 67108864,
+  "sck_frequency": 8000000,
+  "address_mode": "MODE24BIT",
+  "readoc": "READ4IO",
+  "writeoc": "PP4IO",
+  "pp_size": "PPSIZE256",
+  "sck_delay": 128,
+  "rx_delay": 2,
+  "page_size": 4096
+}

boards/nordic/nrf5340dk/board.cmake

@@ -5,6 +5,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS)
 endif()
 
 if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS)
+  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/support/nrf5340dk_qspi_nrfutil_config.json")
   board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
 endif()
 

boards/nordic/nrf5340dk/support/nrf5340dk_qspi_nrfutil_config.json

@@ -0,0 +1,22 @@
+{
+  "firmware_config": {
+    "peripheral": "QSPI"
+  },
+  "pins": {
+    "sck": 17,
+    "csn": 18,
+    "io0": 13,
+    "io1": 14,
+    "io2": 15,
+    "io3": 16
+  },
+  "flash_size": 67108864,
+  "sck_frequency": 8000000,
+  "address_mode": "MODE24BIT",
+  "readoc": "READ4IO",
+  "writeoc": "PP4IO",
+  "pp_size": "PPSIZE256",
+  "sck_delay": 128,
+  "rx_delay": 2,
+  "page_size": 4096
+}

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -7,44 +7,44 @@
 
 / {
 	reserved-memory {
-		cpurad_ram0x_region: memory@2f010000 {
+		cpuapp_ram0x_region: memory@2f010000 {
 			compatible = "nordic,owned-memory";
-			reg = <0x2f010000 DT_SIZE_K(4)>;
+			reg = <0x2f010000 DT_SIZE_K(260)>;
 			status = "disabled";
-			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
+			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x2f010000 0x1000>;
+			ranges = <0x0 0x2f010000 0x41000>;
 
-			cpusec_cpurad_ipc_shm: memory@0 {
+			cpusec_cpuapp_ipc_shm: memory@0 {
 				reg = <0x0 DT_SIZE_K(2)>;
 			};
 
-			cpurad_cpusec_ipc_shm: memory@800 {
+			cpuapp_cpusec_ipc_shm: memory@800 {
 				reg = <0x800 DT_SIZE_K(2)>;
 			};
+
+			cpuapp_data: memory@1000 {
+				reg = <0x1000 DT_SIZE_K(256)>;
+			};
 		};
 
-		cpuapp_ram0x_region: memory@2f011000 {
+		cpurad_ram0x_region: memory@2f051000 {
 			compatible = "nordic,owned-memory";
-			reg = <0x2f011000 DT_SIZE_K(260)>;
+			reg = <0x2f051000 DT_SIZE_K(4)>;
 			status = "disabled";
-			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
+			nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x2f011000 0x41000>;
+			ranges = <0x0 0x2f051000 0x1000>;
 
-			cpusec_cpuapp_ipc_shm: memory@0 {
+			cpusec_cpurad_ipc_shm: memory@0 {
 				reg = <0x0 DT_SIZE_K(2)>;
 			};
 
-			cpuapp_cpusec_ipc_shm: memory@800 {
+			cpurad_cpusec_ipc_shm: memory@800 {
 				reg = <0x800 DT_SIZE_K(2)>;
 			};
-
-			cpuapp_data: memory@1000 {
-				reg = <0x1000 DT_SIZE_K(256)>;
-			};
 		};
 
 		etr_buf_ram0x_region: memory@2f0be000 {

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts

@@ -268,7 +268,7 @@ ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 
 	mx25uw63: mx25uw6345g@0 {
-		compatible = "jedec,mspi-nor";
+		compatible = "mxicy,mx25u", "jedec,mspi-nor";
 		status = "disabled";
 		reg = <0>;
 		jedec-id = [c2 84 37];

boards/nordic/nrf7002dk/board.cmake

@@ -10,7 +10,7 @@ if(CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP OR
    CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NS OR
    CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001 OR
    CONFIG_BOARD_NRF7002DK_NRF5340_CPUAPP_NRF7001_NS)
-  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/nrf7002dk_spi_nrfutil_config.json")
+  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/support/nrf7002dk_spi_nrfutil_config.json")
   board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
 endif()
 

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts

@@ -254,7 +254,7 @@ ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 
 	mx25uw63: mx25uw6345g@0 {
-		compatible = "jedec,mspi-nor";
+		compatible = "mxicy,mx25u", "jedec,mspi-nor";
 		status = "disabled";
 		reg = <0>;
 		jedec-id = [c2 84 37];

boards/nordic/thingy53/board.cmake

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS)
-  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/thingy53_qspi_nrfutil_config.json")
+  board_runner_args(nrfutil "--ext-mem-config-file=${BOARD_DIR}/support/thingy53_qspi_nrfutil_config.json")
   board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
 elseif(CONFIG_BOARD_THINGY53_NRF5340_CPUNET)
   board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")

drivers/clock_control/Kconfig.nrf

@@ -128,6 +128,29 @@ config CLOCK_CONTROL_NRF_USES_TEMP_SENSOR
 endif # CLOCK_CONTROL_NRF_DRIVER_CALIBRATION
 endif # CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION
 
+config CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+	bool "HFINT clock calibration"
+	depends on SOC_NRF54L05 || SOC_NRF54L10 || SOC_NRF54L15
+	depends on DT_HAS_NORDIC_NRF_HFXO_ENABLED
+	depends on !TRUSTED_EXECUTION_NONSECURE
+	select EXPERIMENTAL
+	help
+	  Enables calibration of HFINT clock on every start of HFXO clock.
+
+if CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
+config CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD
+	int "HFINT clock calibration period in milliseconds"
+	default 60000
+	help
+	  Periodically, HFINT clock calibration is performed.
+	  This includes requesting HFXO clock and starting actual calibration.
+	  Once the calibration is finished, the HFXO clock is released.
+	  Set to 0 to disable periodic calibration - in such case calibration
+	  will be done only when HFXO is started by the application itself.
+
+endif # CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
 choice CLOCK_CONTROL_NRF_ACCURACY_PPM
 	prompt "32KHz clock accuracy"
 	default CLOCK_CONTROL_NRF_K32SRC_500PPM if CLOCK_CONTROL_NRF_K32SRC_RC && SOC_COMPATIBLE_NRF52X

drivers/clock_control/clock_control_nrf.c

@@ -14,6 +14,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/shell/shell.h>
 #include <zephyr/irq.h>
+#include <nrf_erratas.h>
 
 LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
 
@@ -172,9 +173,90 @@ static void set_on_state(uint32_t *flags)
 	irq_unlock(key);
 }
 
+#ifdef CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+
+static void nrf54l_errata_30_workaround(void)
+{
+	while (FIELD_GET(CLOCK_XO_STAT_STATE_Msk, NRF_CLOCK->XO.STAT) !=
+	       CLOCK_XO_STAT_STATE_Running) {
+	}
+	const uint32_t higher_bits = *((volatile uint32_t *)0x50120820UL) & 0xFFFFFFC0;
+	*((volatile uint32_t *)0x50120864UL) = 1 | BIT(31);
+	*((volatile uint32_t *)0x50120848UL) = 1;
+	uint32_t off_abs = 24;
+
+	while (off_abs >= 24) {
+		*((volatile uint32_t *)0x50120844UL) = 1;
+		while (((*((volatile uint32_t *)0x50120840UL)) & (1 << 16)) != 0) {
+		}
+		const uint32_t current_cal = *((volatile uint32_t *)0x50120820UL) & 0x3F;
+		const uint32_t cal_result = *((volatile uint32_t *)0x50120840UL) & 0x7FF;
+		int32_t off = 1024 - cal_result;
+
+		off_abs = (off < 0) ? -off : off;
+
+		if (off >= 24 && current_cal < 0x3F) {
+			*((volatile uint32_t *)0x50120820UL) = higher_bits | (current_cal + 1);
+		} else if (off <= -24 && current_cal > 0) {
+			*((volatile uint32_t *)0x50120820UL) = higher_bits | (current_cal - 1);
+		}
+	}
+
+	*((volatile uint32_t *)0x50120848UL) = 0;
+	*((volatile uint32_t *)0x50120864UL) = 0;
+}
+
+#if CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD
+
+static struct onoff_client hf_cal_cli;
+
+static void calibration_finished_callback(struct onoff_manager *mgr,
+					  struct onoff_client *cli,
+					  uint32_t state,
+					  int res)
+{
+	(void)onoff_cancel_or_release(mgr, cli);
+}
+
+static void calibration_handler(struct k_timer *timer)
+{
+	nrf_clock_hfclk_t clk_src;
+
+	bool ret = nrfx_clock_is_running(NRF_CLOCK_DOMAIN_HFCLK, &clk_src);
+
+	if (ret && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY)) {
+		return;
+	}
+
+	sys_notify_init_callback(&hf_cal_cli.notify, calibration_finished_callback);
+	(void)onoff_request(z_nrf_clock_control_get_onoff(CLOCK_CONTROL_NRF_SUBSYS_HF),
+			    &hf_cal_cli);
+}
+
+static K_TIMER_DEFINE(calibration_timer, calibration_handler, NULL);
+
+static int calibration_init(void)
+{
+	k_timer_start(&calibration_timer,
+		      K_NO_WAIT,
+		      K_MSEC(CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD));
+
+	return 0;
+}
+
+SYS_INIT(calibration_init, APPLICATION, 0);
+
+#endif /* CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION_PERIOD */
+#endif /* CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION */
+
 static void clkstarted_handle(const struct device *dev,
 			      enum clock_control_nrf_type type)
 {
+#if CONFIG_CLOCK_CONTROL_NRF_HFINT_CALIBRATION
+	if (nrf54l_errata_30() && (type == CLOCK_CONTROL_NRF_TYPE_HFCLK)) {
+		nrf54l_errata_30_workaround();
+	}
+#endif
 	struct nrf_clock_control_sub_data *sub_data = get_sub_data(dev, type);
 	clock_control_cb_t callback = sub_data->cb;
 	void *user_data = sub_data->user_data;
@@ -599,6 +681,17 @@ static void clock_event_handler(nrfx_clock_evt_type_t event)
 	const struct device *dev = CLOCK_DEVICE;
 
 	switch (event) {
+#if NRF_CLOCK_HAS_XO_TUNE
+	case NRFX_CLOCK_EVT_XO_TUNED:
+		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK);
+		break;
+	case NRFX_CLOCK_EVT_HFCLK_STARTED:
+		/* HFCLK is stable after XOTUNED event.
+		 * HFCLK_STARTED means only that clock has been started.
+		 */
+		break;
+#else
+	/* HFCLK started should be used only if tune operation is done implicitly. */
 	case NRFX_CLOCK_EVT_HFCLK_STARTED:
 	{
 		struct nrf_clock_control_sub_data *data =
@@ -613,6 +706,8 @@ static void clock_event_handler(nrfx_clock_evt_type_t event)
 
 		break;
 	}
+#endif
+
 #if NRF_CLOCK_HAS_HFCLK192M
 	case NRFX_CLOCK_EVT_HFCLK192M_STARTED:
 		clkstarted_handle(dev, CLOCK_CONTROL_NRF_TYPE_HFCLK192M);
@@ -643,7 +738,6 @@ static void clock_event_handler(nrfx_clock_evt_type_t event)
 	case NRFX_CLOCK_EVT_PLL_STARTED:
 #endif
 #if NRF_CLOCK_HAS_XO_TUNE
-	case NRFX_CLOCK_EVT_XO_TUNED:
 	case NRFX_CLOCK_EVT_XO_TUNE_ERROR:
 	case NRFX_CLOCK_EVT_XO_TUNE_FAILED:
 #endif