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FPGA: replace Agilex™ with Agilex® (#1372)
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‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/anr/README.md‎

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@@ -37,7 +37,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -151,7 +151,7 @@ The design uses the following generic header files.
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
@@ -195,7 +195,7 @@ The design uses the following generic header files.
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/board_test/README.md‎

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@@ -40,7 +40,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -122,7 +122,7 @@ Performance results are based on testing as of Jan 31, 2022.
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
@@ -162,7 +162,7 @@ Performance results are based on testing as of Jan 31, 2022.
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky/README.md‎

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@@ -44,7 +44,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -143,7 +143,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and `
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
@@ -187,7 +187,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, and `
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/cholesky_inversion/README.md‎

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -165,7 +165,7 @@ Additionaly, the cmake build system can be configured using the following parame
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/crr/README.md‎

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@@ -39,7 +39,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -153,7 +153,7 @@ This design measures the FPGA performance to determine how many assets can be pr
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/db/README.md‎

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@@ -40,7 +40,7 @@ You can also find more information about [troubleshooting build errors](/DirectP
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| Optimized for | Description
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--- |---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -146,7 +146,7 @@ Query 12 showcases the `MergeJoin` database operator. The block diagram of the d
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the default target (the Agilex™ device family).
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2. Configure the build system for the default target (the Agilex® device family).
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```
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mkdir build
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cd build
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the default target (the Agilex™ device family).
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2. Configure the build system for the default target (the Agilex® device family).
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/decompress/README.md‎

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -304,7 +304,7 @@ For `constexpr_math.hpp`, `memory_utils.hpp`, `metaprogramming_utils.hpp`, `tupl
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/gzip/README.md‎

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
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The GZIP DEFLATE algorithm uses a GZIP-compatible Limpel-Ziv 77 (LZ77) algorithm for data de-duplication and a GZIP-compatible Static Huffman algorithm for bit reduction. The implementation includes three FPGA accelerated tasks (LZ77, Static Huffman, and CRC).
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The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target an Intel® Arria® 10 FPGA. Two engines are created when compiling for Intel® Stratix® 10 or Agilex™ FPGAs, which are a larger device.
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The FPGA implementation of the algorithm enables either one or two independent GZIP compute engines to operate in parallel on the FPGA. The available FPGA resources constrain the number of engines. By default, the design is parameterized to create a single engine when the design is compiled to target an Intel® Arria® 10 FPGA. Two engines are created when compiling for Intel® Stratix® 10 or Agilex® FPGAs, which are a larger device.
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This reference design contains two variants: "High Bandwidth" and "Low-Latency."
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build
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cd build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/merge_sort/README.md‎

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15
44-
| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
44+
| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
4545
| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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```
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mkdir build

‎DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/mvdr_beamforming/README.md‎

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| Optimized for | Description
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|:--- |:---
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| OS | Ubuntu* 18.04/20.04 <br> RHEL*/CentOS* 8 <br> SUSE* 15 <br> Windows* 10
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| Hardware | Intel® Agilex™, Arria® 10, and Stratix® 10 FPGAs
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| Hardware | Intel® Agilex®, Arria® 10, and Stratix® 10 FPGAs
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| Software | Intel® oneAPI DPC++/C++ Compiler
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> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for emulation, generating reports and generating RTL, there are extra software requirements for the simulation flow and FPGA compiles.
@@ -121,7 +121,7 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl
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### On Linux*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
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126126
```
127127
mkdir build
@@ -165,7 +165,7 @@ The `DataProducer` kernel replaces the input IO pipe in the first image. The spl
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### On Windows*
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1. Change to the sample directory.
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2. Configure the build system for the Agilex™ device family, which is the default.
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2. Configure the build system for the Agilex® device family, which is the default.
169169
```
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mkdir build
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cd build

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