Skip to content

Commit ccac7aa

Browse files
Dong BoRealFYang
Dong Bo
authored and
RealFYang
committed
8258932: AArch64: Enhance floating-point Min/MaxReductionV with fminp/fmaxp
Reviewed-by: aph
1 parent 4c75d14 commit ccac7aa

File tree

7 files changed

+565
-432
lines changed

7 files changed

+565
-432
lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -17110,98 +17110,6 @@ instruct reduce_mul2D(vRegD dst, vRegD dsrc, vecX vsrc, vecX tmp)
1711017110
ins_pipe(pipe_class_default);
1711117111
%}
1711217112

17113-
instruct reduce_max2F(vRegF dst, vRegF fsrc, vecD vsrc, vecD tmp) %{
17114-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17115-
match(Set dst (MaxReductionV fsrc vsrc));
17116-
ins_cost(INSN_COST);
17117-
effect(TEMP_DEF dst, TEMP tmp);
17118-
format %{ "fmaxs $dst, $fsrc, $vsrc\n\t"
17119-
"ins $tmp, S, $vsrc, 0, 1\n\t"
17120-
"fmaxs $dst, $dst, $tmp\t# max reduction2F" %}
17121-
ins_encode %{
17122-
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg), as_FloatRegister($vsrc$$reg));
17123-
__ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($vsrc$$reg), 0, 1);
17124-
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
17125-
%}
17126-
ins_pipe(pipe_class_default);
17127-
%}
17128-
17129-
instruct reduce_max4F(vRegF dst, vRegF fsrc, vecX vsrc) %{
17130-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17131-
match(Set dst (MaxReductionV fsrc vsrc));
17132-
ins_cost(INSN_COST);
17133-
effect(TEMP_DEF dst);
17134-
format %{ "fmaxv $dst, T4S, $vsrc\n\t"
17135-
"fmaxs $dst, $dst, $fsrc\t# max reduction4F" %}
17136-
ins_encode %{
17137-
__ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
17138-
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
17139-
%}
17140-
ins_pipe(pipe_class_default);
17141-
%}
17142-
17143-
instruct reduce_max2D(vRegD dst, vRegD dsrc, vecX vsrc, vecX tmp) %{
17144-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17145-
match(Set dst (MaxReductionV dsrc vsrc));
17146-
ins_cost(INSN_COST);
17147-
effect(TEMP_DEF dst, TEMP tmp);
17148-
format %{ "fmaxd $dst, $dsrc, $vsrc\n\t"
17149-
"ins $tmp, D, $vsrc, 0, 1\n\t"
17150-
"fmaxd $dst, $dst, $tmp\t# max reduction2D" %}
17151-
ins_encode %{
17152-
__ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dsrc$$reg), as_FloatRegister($vsrc$$reg));
17153-
__ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($vsrc$$reg), 0, 1);
17154-
__ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
17155-
%}
17156-
ins_pipe(pipe_class_default);
17157-
%}
17158-
17159-
instruct reduce_min2F(vRegF dst, vRegF fsrc, vecD vsrc, vecD tmp) %{
17160-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17161-
match(Set dst (MinReductionV fsrc vsrc));
17162-
ins_cost(INSN_COST);
17163-
effect(TEMP_DEF dst, TEMP tmp);
17164-
format %{ "fmins $dst, $fsrc, $vsrc\n\t"
17165-
"ins $tmp, S, $vsrc, 0, 1\n\t"
17166-
"fmins $dst, $dst, $tmp\t# min reduction2F" %}
17167-
ins_encode %{
17168-
__ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg), as_FloatRegister($vsrc$$reg));
17169-
__ ins(as_FloatRegister($tmp$$reg), __ S, as_FloatRegister($vsrc$$reg), 0, 1);
17170-
__ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
17171-
%}
17172-
ins_pipe(pipe_class_default);
17173-
%}
17174-
17175-
instruct reduce_min4F(vRegF dst, vRegF fsrc, vecX vsrc) %{
17176-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
17177-
match(Set dst (MinReductionV fsrc vsrc));
17178-
ins_cost(INSN_COST);
17179-
effect(TEMP_DEF dst);
17180-
format %{ "fminv $dst, T4S, $vsrc\n\t"
17181-
"fmins $dst, $dst, $fsrc\t# min reduction4F" %}
17182-
ins_encode %{
17183-
__ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
17184-
__ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
17185-
%}
17186-
ins_pipe(pipe_class_default);
17187-
%}
17188-
17189-
instruct reduce_min2D(vRegD dst, vRegD dsrc, vecX vsrc, vecX tmp) %{
17190-
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
17191-
match(Set dst (MinReductionV dsrc vsrc));
17192-
ins_cost(INSN_COST);
17193-
effect(TEMP_DEF dst, TEMP tmp);
17194-
format %{ "fmind $dst, $dsrc, $vsrc\n\t"
17195-
"ins $tmp, D, $vsrc, 0, 1\n\t"
17196-
"fmind $dst, $dst, $tmp\t# min reduction2D" %}
17197-
ins_encode %{
17198-
__ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dsrc$$reg), as_FloatRegister($vsrc$$reg));
17199-
__ ins(as_FloatRegister($tmp$$reg), __ D, as_FloatRegister($vsrc$$reg), 0, 1);
17200-
__ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
17201-
%}
17202-
ins_pipe(pipe_class_default);
17203-
%}
17204-
1720517113
// ====================VECTOR ARITHMETIC=======================================
1720617114

1720717115
// --------------------------------- ADD --------------------------------------

‎src/hotspot/cpu/aarch64/aarch64_neon.ad‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -899,6 +899,90 @@ instruct reduce_min2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlag
899899
ins_pipe(pipe_slow);
900900
%}
901901

902+
instruct reduce_max2F(vRegF dst, vRegF fsrc, vecD vsrc) %{
903+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
904+
match(Set dst (MaxReductionV fsrc vsrc));
905+
ins_cost(INSN_COST);
906+
effect(TEMP_DEF dst);
907+
format %{ "fmaxp $dst, $vsrc, S\n\t"
908+
"fmaxs $dst, $dst, $fsrc\t# max reduction2F" %}
909+
ins_encode %{
910+
__ fmaxp(as_FloatRegister($dst$$reg), as_FloatRegister($vsrc$$reg), __ S);
911+
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
912+
%}
913+
ins_pipe(pipe_class_default);
914+
%}
915+
916+
instruct reduce_max4F(vRegF dst, vRegF fsrc, vecX vsrc) %{
917+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
918+
match(Set dst (MaxReductionV fsrc vsrc));
919+
ins_cost(INSN_COST);
920+
effect(TEMP_DEF dst);
921+
format %{ "fmaxv $dst, T4S, $vsrc\n\t"
922+
"fmaxs $dst, $dst, $fsrc\t# max reduction4F" %}
923+
ins_encode %{
924+
__ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
925+
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
926+
%}
927+
ins_pipe(pipe_class_default);
928+
%}
929+
930+
instruct reduce_max2D(vRegD dst, vRegD dsrc, vecX vsrc) %{
931+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
932+
match(Set dst (MaxReductionV dsrc vsrc));
933+
ins_cost(INSN_COST);
934+
effect(TEMP_DEF dst);
935+
format %{ "fmaxp $dst, $vsrc, D\n\t"
936+
"fmaxd $dst, $dst, $dsrc\t# max reduction2D" %}
937+
ins_encode %{
938+
__ fmaxp(as_FloatRegister($dst$$reg), as_FloatRegister($vsrc$$reg), __ D);
939+
__ fmaxd(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($dsrc$$reg));
940+
%}
941+
ins_pipe(pipe_class_default);
942+
%}
943+
944+
instruct reduce_min2F(vRegF dst, vRegF fsrc, vecD vsrc) %{
945+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
946+
match(Set dst (MinReductionV fsrc vsrc));
947+
ins_cost(INSN_COST);
948+
effect(TEMP_DEF dst);
949+
format %{ "fminp $dst, $vsrc, S\n\t"
950+
"fmins $dst, $dst, $fsrc\t# min reduction2F" %}
951+
ins_encode %{
952+
__ fminp(as_FloatRegister($dst$$reg), as_FloatRegister($vsrc$$reg), __ S);
953+
__ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
954+
%}
955+
ins_pipe(pipe_class_default);
956+
%}
957+
958+
instruct reduce_min4F(vRegF dst, vRegF fsrc, vecX vsrc) %{
959+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
960+
match(Set dst (MinReductionV fsrc vsrc));
961+
ins_cost(INSN_COST);
962+
effect(TEMP_DEF dst);
963+
format %{ "fminv $dst, T4S, $vsrc\n\t"
964+
"fmins $dst, $dst, $fsrc\t# min reduction4F" %}
965+
ins_encode %{
966+
__ fminv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
967+
__ fmins(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
968+
%}
969+
ins_pipe(pipe_class_default);
970+
%}
971+
972+
instruct reduce_min2D(vRegD dst, vRegD dsrc, vecX vsrc) %{
973+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
974+
match(Set dst (MinReductionV dsrc vsrc));
975+
ins_cost(INSN_COST);
976+
effect(TEMP_DEF dst);
977+
format %{ "fminp $dst, $vsrc, D\n\t"
978+
"fmind $dst, $dst, $dsrc\t# min reduction2D" %}
979+
ins_encode %{
980+
__ fminp(as_FloatRegister($dst$$reg), as_FloatRegister($vsrc$$reg), __ D);
981+
__ fmind(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($dsrc$$reg));
982+
%}
983+
ins_pipe(pipe_class_default);
984+
%}
985+
902986
instruct reduce_and8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
903987
%{
904988
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);

‎src/hotspot/cpu/aarch64/aarch64_neon_ad.m4‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -536,6 +536,30 @@ dnl $1 $2 $3
536536
REDUCE_MAX_MIN_2L(max, Max, GT)
537537
REDUCE_MAX_MIN_2L(min, Min, LT)
538538
dnl
539+
define(`REDUCE_MINMAX_FORD', `
540+
instruct reduce_$1$4$5(vReg$5 dst, vReg$5 $6src, vec$7 vsrc) %{
541+
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_`'ifelse($5, F, FLOAT, DOUBLE));
542+
match(Set dst (ifelse($1, max, Max, Min)ReductionV $6src vsrc));
543+
ins_cost(INSN_COST);
544+
effect(TEMP_DEF dst);
545+
format %{ "$2 $dst, ifelse($4, 2, $vsrc`, 'ifelse($5, F, S, D), ` T4S, $vsrc')\n\t"
546+
"$3 $dst, $dst, $$6src\t# $1 reduction$4$5" %}
547+
ins_encode %{
548+
__ $2(as_FloatRegister($dst$$reg), ifelse($4, 4, `__ T4S, as_FloatRegister($vsrc$$reg))',
549+
$4$5, 2F, `as_FloatRegister($vsrc$$reg), __ S)',
550+
$4$5, 2D, `as_FloatRegister($vsrc$$reg), __ D)');
551+
__ $3(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($$6src$$reg));
552+
%}
553+
ins_pipe(pipe_class_default);
554+
%}')dnl
555+
dnl $1 $2 $3 $4 $5 $6 $7
556+
REDUCE_MINMAX_FORD(max, fmaxp, fmaxs, 2, F, f, D)
557+
REDUCE_MINMAX_FORD(max, fmaxv, fmaxs, 4, F, f, X)
558+
REDUCE_MINMAX_FORD(max, fmaxp, fmaxd, 2, D, d, X)
559+
REDUCE_MINMAX_FORD(min, fminp, fmins, 2, F, f, D)
560+
REDUCE_MINMAX_FORD(min, fminv, fmins, 4, F, f, X)
561+
REDUCE_MINMAX_FORD(min, fminp, fmind, 2, D, d, X)
562+
dnl
539563
define(`REDUCE_LOGIC_OP_8B', `
540564
instruct reduce_$1`'8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
541565
%{

‎src/hotspot/cpu/aarch64/assembler_aarch64.hpp‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2635,16 +2635,21 @@ void mvnw(Register Rd, Register Rm,
26352635
rf(Vn, 5), rf(Vd, 0);
26362636
}
26372637

2638-
// (Floating-point) {a, b} -> (a + b)
2639-
void faddp(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2640-
assert(type == D || type == S, "Wrong type for faddp");
2641-
starti;
2642-
f(0b011111100, 31, 23);
2643-
f(type == D ? 1 : 0, 22);
2644-
f(0b110000110110, 21, 10);
2645-
rf(Vn, 5), rf(Vd, 0);
2638+
// Floating-point AdvSIMD scalar pairwise
2639+
#define INSN(NAME, op1, op2) \
2640+
void NAME(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) { \
2641+
starti; \
2642+
assert(type == D || type == S, "Wrong type for faddp/fmaxp/fminp"); \
2643+
f(0b0111111, 31, 25), f(op1, 24, 23), \
2644+
f(type == S ? 0 : 1, 22), f(0b11000, 21, 17), f(op2, 16, 10), rf(Vn, 5), rf(Vd, 0); \
26462645
}
26472646

2647+
INSN(faddp, 0b00, 0b0110110);
2648+
INSN(fmaxp, 0b00, 0b0111110);
2649+
INSN(fminp, 0b01, 0b0111110);
2650+
2651+
#undef INSN
2652+
26482653
void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
26492654
starti;
26502655
assert(T != Q, "invalid register variant");

‎test/hotspot/gtest/aarch64/aarch64-asmtest.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1401,6 +1401,8 @@ def generate(kind, names):
14011401
["sminv", "sminv", "8B"], ["sminv", "sminv", "16B"],
14021402
["sminv", "sminv", "4H"], ["sminv", "sminv", "8H"],
14031403
["sminv", "sminv", "4S"], ["fminv", "fminv", "4S"],
1404+
["fmaxp", "fmaxp", "2S"], ["fmaxp", "fmaxp", "2D"],
1405+
["fminp", "fminp", "2S"], ["fminp", "fminp", "2D"],
14041406
])
14051407

14061408
generate(TwoRegNEONOp,

0 commit comments

Comments
 (0)