Skip to content

8299847: RISC-V: Improve PrintOptoAssembly output of CMoveI/L nodes #11919

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
RealFYang wants to merge 5 commits into from
Closed

8299847: RISC-V: Improve PrintOptoAssembly output of CMoveI/L nodes #11919

Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
e7ae82f
8299847: RISC-V: Incorrect branch condition code in PrintOptoAssembly…
RealFYang Jan 10, 2023
f28dbcb
Fix
RealFYang Jan 10, 2023
8e4b4c5
Fix
RealFYang Jan 13, 2023
c36203c
Merge branch 'master' into JDK-8299847
RealFYang Jan 16, 2023
08318af
Comment
RealFYang Jan 16, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
69 changes: 29 additions & 40 deletions src/hotspot/cpu/riscv/riscv.ad
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -940,7 +940,7 @@ definitions %{
int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
int_def BRANCH_COST ( 100, 1 * DEFAULT_COST); // branch, jmp, call
int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi
int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi
Expand Down Expand Up @@ -3817,13 +3817,13 @@ operand cmpOpULtGe()
format %{ "" %}
interface(COND_INTER) %{
equal(0x0, "eq");
greater(0x1, "gt");
greater(0x1, "gtu");
overflow(0x2, "overflow");
less(0x3, "lt");
less(0x3, "ltu");
not_equal(0x4, "ne");
less_equal(0x5, "le");
less_equal(0x5, "leu");
no_overflow(0x6, "no_overflow");
greater_equal(0x7, "ge");
greater_equal(0x7, "geu");
%}
%}

Expand All @@ -3839,13 +3839,13 @@ operand cmpOpUEqNeLeGt()
format %{ "" %}
interface(COND_INTER) %{
equal(0x0, "eq");
greater(0x1, "gt");
greater(0x1, "gtu");
overflow(0x2, "overflow");
less(0x3, "lt");
less(0x3, "ltu");
not_equal(0x4, "ne");
less_equal(0x5, "le");
less_equal(0x5, "leu");
no_overflow(0x6, "no_overflow");
greater_equal(0x7, "ge");
greater_equal(0x7, "geu");
%}
%}

Expand Down Expand Up @@ -4373,7 +4373,7 @@ pipe_class istore_reg_reg(iRegI dst, iRegI src)
LDST : MEM;
%}

//------- Store pipeline operations -----------------------
//------- Control transfer pipeline operations ------------

// Branch
pipe_class pipe_branch()
Expand Down Expand Up @@ -9890,112 +9890,101 @@ instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}

instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}

instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}

instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}

instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}

instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
ins_cost(ALU_COST + BRANCH_COST);

format %{
"bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
"mv $dst, $src\n\t"
"skip:"
%}
"CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
%}

ins_encode %{
__ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
as_Register($op1$$reg), as_Register($op2$$reg),
as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(pipe_slow);
ins_pipe(pipe_class_compare);
%}


Expand Down