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8325589: C2 SuperWord refactoring: create VLoopAnalyzer with Submodules #17800

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8325589: C2 SuperWord refactoring: create VLoopAnalyzer with Submodules #17800

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3d7bca8
8325589
eme64 Feb 10, 2024
4fcbad6
VLoopReductions
eme64 Feb 10, 2024
760b379
VLoopMemorySlices
eme64 Feb 10, 2024
8e43774
VLoopBody
eme64 Feb 10, 2024
3cf41a5
VLoopTypes
eme64 Feb 10, 2024
a69bacf
remove some comments
eme64 Feb 10, 2024
b43d513
move _loop_or_ctrl from ResouceArena, bc ResourceMark in SuperWord::d…
eme64 Feb 11, 2024
9a485b0
manual merge
eme64 Feb 13, 2024
19acaef
VStatus
eme64 Feb 14, 2024
6c28172
Apply suggestions from code review
eme64 Feb 14, 2024
ba07a79
more for Christian
eme64 Feb 14, 2024
1d771fd
remove accessors, use fields instead
eme64 Feb 15, 2024
77695f0
indentation
eme64 Feb 15, 2024
9c70b2d
review updates for Christian
eme64 Feb 26, 2024
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16 changes: 8 additions & 8 deletions src/hotspot/cpu/x86/x86_64.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -4480,7 +4480,7 @@ instruct loadD(regD dst, memory mem)

// max = java.lang.Math.max(float a, float b)
instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
match(Set dst (MaxF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{ "maxF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
Expand All @@ -4491,7 +4491,7 @@ instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp,
%}

instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
predicate(UseAVX > 0 && SuperWord::is_reduction(n));
predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
match(Set dst (MaxF a b));
effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);

Expand All @@ -4505,7 +4505,7 @@ instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRe

// max = java.lang.Math.max(double a, double b)
instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
match(Set dst (MaxD a b));
effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
format %{ "maxD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
Expand All @@ -4516,7 +4516,7 @@ instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
%}

instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
predicate(UseAVX > 0 && SuperWord::is_reduction(n));
predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
match(Set dst (MaxD a b));
effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);

Expand All @@ -4530,7 +4530,7 @@ instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRe

// min = java.lang.Math.min(float a, float b)
instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
match(Set dst (MinF a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{ "minF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
Expand All @@ -4541,7 +4541,7 @@ instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp,
%}

instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
predicate(UseAVX > 0 && SuperWord::is_reduction(n));
predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
match(Set dst (MinF a b));
effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);

Expand All @@ -4555,7 +4555,7 @@ instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRe

// min = java.lang.Math.min(double a, double b)
instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
match(Set dst (MinD a b));
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
format %{ "minD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
Expand All @@ -4566,7 +4566,7 @@ instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
%}

instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
predicate(UseAVX > 0 && SuperWord::is_reduction(n));
predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
match(Set dst (MinD a b));
effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);

Expand Down
7 changes: 6 additions & 1 deletion src/hotspot/share/opto/loopopts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4232,7 +4232,12 @@ PhaseIdealLoop::auto_vectorize(IdealLoopTree* lpt, VSharedData &vshared) {
// Ensure the shared data is cleared before each use
vshared.clear();

SuperWord sw(vloop, vshared);
const VLoopAnalyzer vloop_analyzer(vloop, vshared);
if (!vloop_analyzer.success()) {
return AutoVectorizeStatus::TriedAndFailed;
}

SuperWord sw(vloop_analyzer);
if (!sw.transform_loop()) {
return AutoVectorizeStatus::TriedAndFailed;
}
Expand Down
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