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8349632: RISC-V: Add Zfa fminm/fmaxm #23509

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8349632: RISC-V: Add Zfa fminm/fmaxm #23509

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02e1562
8349632:RISC-V: Add Zfa fminm/fmaxm
Anjian-Wen Feb 6, 2025
1d22e6f
JDK-8349632: RISCV: Add Zfa fminm/fmaxm
Anjian-Wen Feb 21, 2025
defa74d
8349632: RISC-V: Add Zfa fminm/fmaxm
Anjian-Wen Feb 21, 2025
037a364
JDK-8349632: RISC-V: Add Zfa fminm/fmaxm
Anjian-Wen Feb 21, 2025
b763ee4
8349632: RISC-V: Add Zfa fminm/fmaxm
Anjian-Wen Feb 24, 2025
927d024
Merge branch 'openjdk:master' into Zfa_dev_branch
Anjian-Wen Mar 12, 2025
faa9070
add temp commit for test
Anjian-Wen Mar 12, 2025
249bcd4
delete useless comment
Anjian-Wen Mar 12, 2025
c65798a
Merge branch 'openjdk:master' into Zfa_dev_branch
Anjian-Wen Mar 14, 2025
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20 changes: 20 additions & 0 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1450,6 +1450,26 @@ enum operand_size { int8, int16, int32, uint32, int64 };
fp_base<D_64_dp, 0b11110>(Rd, Rs1, 0b00001, 0b000);
}

void fminm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b010);
}

void fmaxm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b011);
}

void fminm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b010);
}

void fmaxm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b011);
}

// ==========================
// RISC-V Vector Extension
// ==========================
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60 changes: 60 additions & 0 deletions src/hotspot/cpu/riscv/riscv.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -7349,6 +7349,7 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{

// Math.max(FF)F
instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
predicate(!UseZfa);
match(Set dst (MaxF src1 src2));
effect(KILL cr);

Expand All @@ -7363,8 +7364,23 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
ins_pipe(pipe_class_default);
%}

instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
predicate(UseZfa);
match(Set dst (MaxF src1 src2));

format %{ "maxF $dst, $src1, $src2" %}

ins_encode %{
__ fmaxm_s(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}

ins_pipe(pipe_class_default);
%}

// Math.min(FF)F
instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
predicate(!UseZfa);
match(Set dst (MinF src1 src2));
effect(KILL cr);

Expand All @@ -7379,8 +7395,23 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
ins_pipe(pipe_class_default);
%}

instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
predicate(UseZfa);
match(Set dst (MinF src1 src2));

format %{ "minF $dst, $src1, $src2" %}

ins_encode %{
__ fminm_s(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}

ins_pipe(pipe_class_default);
%}

// Math.max(DD)D
instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
predicate(!UseZfa);
match(Set dst (MaxD src1 src2));
effect(KILL cr);

Expand All @@ -7395,8 +7426,23 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
ins_pipe(pipe_class_default);
%}

instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
predicate(UseZfa);
match(Set dst (MaxD src1 src2));

format %{ "maxD $dst, $src1, $src2" %}

ins_encode %{
__ fmaxm_d(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}

ins_pipe(pipe_class_default);
%}

// Math.min(DD)D
instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
predicate(!UseZfa);
match(Set dst (MinD src1 src2));
effect(KILL cr);

Expand All @@ -7411,6 +7457,20 @@ instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
ins_pipe(pipe_class_default);
%}

instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
predicate(UseZfa);
match(Set dst (MinD src1 src2));

format %{ "minD $dst, $src1, $src2" %}

ins_encode %{
__ fminm_d(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}

ins_pipe(pipe_class_default);
%}

// Float.isInfinite
instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
%{
Expand Down