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Merged
merged 17 commits into from
Nov 14, 2025
Merged

[pull] main from llvm:main #698

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d719876
[clang-format] Recognize Verilog DPI export and import (#165595)
sstwcw Nov 13, 2025
f93fcde
[offload-arch] Fix amdgpu-arch crash on Windows with ROCm 7.1 (#167695)
yxsamliu Nov 14, 2025
4fe79a7
[sanitizer-common] [Darwin] Fix overlapping dyld segment addresses (a…
ndrewh Nov 14, 2025
cdbf243
[clang] Add a TODO for output paths in invocation path visitation (#1…
jansvoboda11 Nov 14, 2025
630dfc9
[dfsan] Fix Endianess issue (#162881)
anoopkg6 Nov 14, 2025
b1262d1
[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands…
Muzammiluddin-Syed-ECE Nov 14, 2025
cfad41c
[CIR] Upstream l-value emission for ExprWithCleanups (#167938)
andykaylor Nov 14, 2025
182c415
AMDGPU: Remove getProperlyAlignedRC (#167993)
arsenm Nov 14, 2025
376312a
[Hexagon] Implement isUsedByReturnOnly (#167637)
svs-quic Nov 14, 2025
b196c52
[Support][Jobserver][Tests] Simplify default executor init and make (…
yxsamliu Nov 14, 2025
b713484
[libc++][ranges] LWG3505: `split_view::outer-iterator::operator++` mi…
H-G-Hristov Nov 14, 2025
815453f
[profcheck] Disable verification of selects on vector conditions. (#1…
mtrofin Nov 14, 2025
f6004ae
[msan] Support x86_avx512bf16_dpbf16ps (#166862)
thurstond Nov 14, 2025
30d8f69
[msan][NFCI] Generalize handlePairwiseShadowOrIntrinsic to have shard…
thurstond Nov 14, 2025
5f55048
[clang][bytecode] Print field descriptor in Pointer::print() (#168002)
tbaederr Nov 14, 2025
757dc70
[clang-tidy][NFC] Add clang-format option to insert newline at EOF (#…
vbvictor Nov 14, 2025
6b44cea
Revert "[Support][Jobserver][Tests] Simplify default executor init an…
boomanaiden154 Nov 14, 2025
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1 change: 1 addition & 0 deletions clang-tools-extra/clang-tidy/.clang-format
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@@ -1,3 +1,4 @@
BasedOnStyle: LLVM
QualifierAlignment: Left
LineEnding: LF
InsertNewlineAtEOF: true
1 change: 1 addition & 0 deletions clang/include/clang/CIR/MissingFeatures.h
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Expand Up @@ -226,6 +226,7 @@ struct MissingFeatures {
static bool cleanupAppendInsts() { return false; }
static bool cleanupBranchThrough() { return false; }
static bool cleanupIndexAndBIAdjustment() { return false; }
static bool cleanupWithPreservedValues() { return false; }
static bool cleanupsToDeactivate() { return false; }
static bool constEmitterAggILE() { return false; }
static bool constEmitterArrayILE() { return false; }
Expand Down
3 changes: 3 additions & 0 deletions clang/lib/AST/ByteCode/Pointer.h
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Expand Up @@ -830,6 +830,9 @@ class Pointer {

inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const Pointer &P) {
P.print(OS);
OS << ' ';
if (const Descriptor *D = P.getFieldDesc())
D->dump(OS);
return OS;
}

Expand Down
7 changes: 7 additions & 0 deletions clang/lib/CIR/CodeGen/CIRGenFunction.cpp
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Expand Up @@ -921,6 +921,13 @@ LValue CIRGenFunction::emitLValue(const Expr *e) {
case Expr::CXXOperatorCallExprClass:
case Expr::UserDefinedLiteralClass:
return emitCallExprLValue(cast<CallExpr>(e));
case Expr::ExprWithCleanupsClass: {
const auto *cleanups = cast<ExprWithCleanups>(e);
RunCleanupsScope scope(*this);
LValue lv = emitLValue(cleanups->getSubExpr());
assert(!cir::MissingFeatures::cleanupWithPreservedValues());
return lv;
}
case Expr::ParenExprClass:
return emitLValue(cast<ParenExpr>(e)->getSubExpr());
case Expr::GenericSelectionExprClass:
Expand Down
182 changes: 137 additions & 45 deletions clang/lib/Format/FormatToken.h
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Expand Up @@ -1170,6 +1170,7 @@ struct AdditionalKeywords {
kw_checker = &IdentTable.get("checker");
kw_clocking = &IdentTable.get("clocking");
kw_constraint = &IdentTable.get("constraint");
kw_context = &IdentTable.get("context");
kw_cover = &IdentTable.get("cover");
kw_covergroup = &IdentTable.get("covergroup");
kw_coverpoint = &IdentTable.get("coverpoint");
Expand Down Expand Up @@ -1325,50 +1326,138 @@ struct AdditionalKeywords {
// Some keywords are not included here because they don't need special
// treatment like `showcancelled` or they should be treated as identifiers
// like `int` and `logic`.
VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
{kw_always, kw_always_comb, kw_always_ff,
kw_always_latch, kw_assert, kw_assign,
kw_assume, kw_automatic, kw_before,
kw_begin, kw_bins, kw_binsof,
kw_casex, kw_casez, kw_celldefine,
kw_checker, kw_clocking, kw_constraint,
kw_cover, kw_covergroup, kw_coverpoint,
kw_disable, kw_dist, kw_edge,
kw_end, kw_endcase, kw_endchecker,
kw_endclass, kw_endclocking, kw_endfunction,
kw_endgenerate, kw_endgroup, kw_endinterface,
kw_endmodule, kw_endpackage, kw_endprimitive,
kw_endprogram, kw_endproperty, kw_endsequence,
kw_endspecify, kw_endtable, kw_endtask,
kw_extends, kw_final, kw_foreach,
kw_forever, kw_fork, kw_function,
kw_generate, kw_highz0, kw_highz1,
kw_iff, kw_ifnone, kw_ignore_bins,
kw_illegal_bins, kw_implements, kw_import,
kw_initial, kw_inout, kw_input,
kw_inside, kw_interconnect, kw_interface,
kw_intersect, kw_join, kw_join_any,
kw_join_none, kw_large, kw_let,
kw_local, kw_localparam, kw_macromodule,
kw_matches, kw_medium, kw_negedge,
kw_output, kw_package, kw_packed,
kw_parameter, kw_posedge, kw_primitive,
kw_priority, kw_program, kw_property,
kw_pull0, kw_pull1, kw_pure,
kw_rand, kw_randc, kw_randcase,
kw_randsequence, kw_ref, kw_repeat,
kw_sample, kw_scalared, kw_sequence,
kw_small, kw_soft, kw_solve,
kw_specify, kw_specparam, kw_strong0,
kw_strong1, kw_supply0, kw_supply1,
kw_table, kw_tagged, kw_task,
kw_tri, kw_tri0, kw_tri1,
kw_triand, kw_trior, kw_trireg,
kw_unique, kw_unique0, kw_uwire,
kw_var, kw_vectored, kw_wait,
kw_wand, kw_weak0, kw_weak1,
kw_wildcard, kw_wire, kw_with,
kw_wor, kw_verilogHash, kw_verilogHashHash});
VerilogExtraKeywords =
std::unordered_set<IdentifierInfo *>({kw_always,
kw_always_comb,
kw_always_ff,
kw_always_latch,
kw_assert,
kw_assign,
kw_assume,
kw_automatic,
kw_before,
kw_begin,
kw_bins,
kw_binsof,
kw_casex,
kw_casez,
kw_celldefine,
kw_checker,
kw_clocking,
kw_constraint,
kw_context,
kw_cover,
kw_covergroup,
kw_coverpoint,
kw_disable,
kw_dist,
kw_edge,
kw_end,
kw_endcase,
kw_endchecker,
kw_endclass,
kw_endclocking,
kw_endfunction,
kw_endgenerate,
kw_endgroup,
kw_endinterface,
kw_endmodule,
kw_endpackage,
kw_endprimitive,
kw_endprogram,
kw_endproperty,
kw_endsequence,
kw_endspecify,
kw_endtable,
kw_endtask,
kw_extends,
kw_final,
kw_foreach,
kw_forever,
kw_fork,
kw_function,
kw_generate,
kw_highz0,
kw_highz1,
kw_iff,
kw_ifnone,
kw_ignore_bins,
kw_illegal_bins,
kw_implements,
kw_import,
kw_initial,
kw_inout,
kw_input,
kw_inside,
kw_interconnect,
kw_interface,
kw_intersect,
kw_join,
kw_join_any,
kw_join_none,
kw_large,
kw_let,
kw_local,
kw_localparam,
kw_macromodule,
kw_matches,
kw_medium,
kw_module,
kw_negedge,
kw_output,
kw_package,
kw_packed,
kw_parameter,
kw_posedge,
kw_primitive,
kw_priority,
kw_program,
kw_property,
kw_pull0,
kw_pull1,
kw_pure,
kw_rand,
kw_randc,
kw_randcase,
kw_randsequence,
kw_ref,
kw_repeat,
kw_sample,
kw_scalared,
kw_sequence,
kw_small,
kw_soft,
kw_solve,
kw_specify,
kw_specparam,
kw_strong0,
kw_strong1,
kw_supply0,
kw_supply1,
kw_table,
kw_tagged,
kw_task,
kw_tri,
kw_tri0,
kw_tri1,
kw_triand,
kw_trior,
kw_trireg,
kw_unique,
kw_unique0,
kw_uwire,
kw_var,
kw_vectored,
kw_wait,
kw_wand,
kw_weak0,
kw_weak1,
kw_wildcard,
kw_wire,
kw_with,
kw_wor,
kw_verilogHash,
kw_verilogHashHash});

TableGenExtraKeywords = std::unordered_set<IdentifierInfo *>({
kw_assert,
Expand Down Expand Up @@ -1516,6 +1605,7 @@ struct AdditionalKeywords {
IdentifierInfo *kw_checker;
IdentifierInfo *kw_clocking;
IdentifierInfo *kw_constraint;
IdentifierInfo *kw_context;
IdentifierInfo *kw_cover;
IdentifierInfo *kw_covergroup;
IdentifierInfo *kw_coverpoint;
Expand Down Expand Up @@ -1800,11 +1890,13 @@ struct AdditionalKeywords {
case tok::kw_continue:
case tok::kw_default:
case tok::kw_do:
case tok::kw_extern:
case tok::kw_else:
case tok::kw_enum:
case tok::kw_export:
case tok::kw_extern:
case tok::kw_for:
case tok::kw_if:
case tok::kw_import:
case tok::kw_restrict:
case tok::kw_signed:
case tok::kw_static:
Expand Down
38 changes: 31 additions & 7 deletions clang/lib/Format/UnwrappedLineParser.cpp
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Expand Up @@ -1592,15 +1592,14 @@ void UnwrappedLineParser::parseStructuralElement(
parseTryCatch();
return;
case tok::kw_extern:
nextToken();
if (Style.isVerilog()) {
// In Verilog and extern module declaration looks like a start of module.
// In Verilog an extern module declaration looks like a start of module.
// But there is no body and endmodule. So we handle it separately.
if (Keywords.isVerilogHierarchy(*FormatTok)) {
parseVerilogHierarchyHeader();
return;
}
} else if (FormatTok->is(tok::string_literal)) {
parseVerilogExtern();
return;
}
nextToken();
if (FormatTok->is(tok::string_literal)) {
nextToken();
if (FormatTok->is(tok::l_brace)) {
if (Style.BraceWrapping.AfterExternBlock)
Expand All @@ -1625,6 +1624,10 @@ void UnwrappedLineParser::parseStructuralElement(
parseJavaScriptEs6ImportExport();
return;
}
if (Style.isVerilog()) {
parseVerilogExtern();
return;
}
if (IsCpp) {
nextToken();
if (FormatTok->is(tok::kw_namespace)) {
Expand Down Expand Up @@ -1673,6 +1676,10 @@ void UnwrappedLineParser::parseStructuralElement(
addUnwrappedLine();
return;
}
if (Style.isVerilog()) {
parseVerilogExtern();
return;
}
if (IsCpp && parseModuleImport())
return;
}
Expand Down Expand Up @@ -4559,6 +4566,23 @@ void UnwrappedLineParser::parseVerilogCaseLabel() {
Line->Level = OrigLevel;
}

void UnwrappedLineParser::parseVerilogExtern() {
assert(
FormatTok->isOneOf(tok::kw_extern, tok::kw_export, Keywords.kw_import));
nextToken();
// "DPI-C"
if (FormatTok->is(tok::string_literal))
nextToken();
if (FormatTok->isOneOf(Keywords.kw_context, Keywords.kw_pure))
nextToken();
if (Keywords.isVerilogIdentifier(*FormatTok))
nextToken();
if (FormatTok->is(tok::equal))
nextToken();
if (Keywords.isVerilogHierarchy(*FormatTok))
parseVerilogHierarchyHeader();
}

bool UnwrappedLineParser::containsExpansion(const UnwrappedLine &Line) const {
for (const auto &N : Line.Tokens) {
if (N.Tok->MacroCtx)
Expand Down
2 changes: 2 additions & 0 deletions clang/lib/Format/UnwrappedLineParser.h
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Expand Up @@ -205,6 +205,8 @@ class UnwrappedLineParser {
unsigned parseVerilogHierarchyHeader();
void parseVerilogTable();
void parseVerilogCaseLabel();
// For import, export, and extern.
void parseVerilogExtern();
std::optional<llvm::SmallVector<llvm::SmallVector<FormatToken *, 8>, 1>>
parseMacroCall();

Expand Down
1 change: 1 addition & 0 deletions clang/lib/Frontend/CompilerInvocation.cpp
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Expand Up @@ -5322,6 +5322,7 @@ void CompilerInvocationBase::visitPathsImpl(

RETURN_IF(Input.File);
}
// TODO: Also report output files such as FrontendOpts.OutputFile;
RETURN_IF(FrontendOpts.CodeCompletionAt.FileName);
RETURN_IF_MANY(FrontendOpts.ModuleMapFiles);
RETURN_IF_MANY(FrontendOpts.ModuleFiles);
Expand Down
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