Debugging a number of proxy issues on a boot that failed to find all the DDR DIMMS, and in the traces, I noticed some strange behavior around fetching:
- We start at addr 0x55 without setting the 0x0b page register.
- Initial write is W[0x55] 0x80, then a big R[0x55]
- Next txn is W[0x55] 0x80, then another big R[0x55]
- Next txn is W[0x55], 0x0B, 0x01 which is moving pages
- normal from this point forward, moving pages.
Then we move through addresses 0x51, 0x52, 0x53, 0x54, 0x55
I think this illustrates a couple of problems:
- We only read 0x51, 0x52, 0x53, 0x54, 0x55 (at least 2x on this one) but should read 6 distinct addresses
- We're making assumptions about the starting page pointer that are potentially incorrect, especially if we fetch again without a power cycle.
Note that this is only related to cache-side and topo issues, SP5's psp not getting correct data is likely something else.