Skip to content

Commit 6fe0050

Browse files
author
Marcos
committed
docs(upstream): litepcie ecp5phy outreach email draft
Drafts the email for Marcos to send personally from m@pop.coop to Florent Kermarrec (LitePCIe maintainer) per the path-1b decision recorded in popsolutions/MAST#13. README of enjoy-digital/litepcie points to florent@enjoy-digital.fr as the maintainer's stated channel for support discussions, and Discussions are not enabled on the repo or sibling repos in the LiteX ecosystem. The doc has three parts: 1. Header making clear this is a DRAFT for Marcos to send, not a public communication from the cooperative. Outlines the draft -> Agent R review -> Marcos sends -> response logged workflow. 2. The email itself: introduces PopSolutions, summarises the day-1 audit findings (missing ecp5pciephy.py, ECP5 has only PCS hard block not full controller, multi-quarter scope), and asks four calibration questions about diagnosis correctness, prior consideration, acceptable initial-PR scope, and whether sponsorship is the right channel. Explicitly normalises rejection ("we don't think this fits") and absent reply as legitimate responses. No timeline committed. 3. Notes for Marcos before sending: voice adaptation, link verification, public-artefact summarisation policy, subject-line guidance. Agent 4 does NOT send mail. Agent 4 does NOT use any sock-puppet account. Once Marcos sends, contribution log file 2026-05-05-litepcie-ecp5phy.md gets updated to awaiting-upstream-feedback in a follow-up PR. Authored by Agent 4 (Upstream Contributions). Signed-off-by: Marcos <m@pop.coop> (cherry picked from commit e2e79d8) Signed-off-by: Marcos <m@pop.coop> Reviewed-by: Agent R (Reviewer) Cherry-picked-via: PR #19 closed without merge due to GitHub --delete-branch race; recovered via local squash
1 parent 8958e36 commit 6fe0050

1 file changed

Lines changed: 160 additions & 0 deletions

File tree

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
1+
<!-- SPDX-License-Identifier: CC-BY-SA-4.0 -->
2+
3+
# 2026-05-05 — LitePCIe ECP5 PHY upstream outreach (DRAFT)
4+
5+
**Status:** Draft — for human review before sending.
6+
7+
## What this is
8+
9+
This document is a **draft email** for Marcos Méndez Quintero
10+
(`m@pop.coop`) to send personally from his mail client to Florent
11+
Kermarrec (LitePCIe maintainer, `florent@enjoy-digital.fr`).
12+
13+
It is **not** a public communication from the cooperative, **not** an
14+
issue, **not** a PR. The cooperative's public artefacts on this topic
15+
are:
16+
17+
- `docs/upstream-contributions/0001-rev-a-known-upstream-issues.md`
18+
(the rev-A survey, on `main`).
19+
- `docs/upstream-contributions/2026-05-05-litepcie-ecp5phy.md` (the
20+
contribution log entry in scoping state, currently on PR #17).
21+
- popsolutions/MAST#13 (the cross-stream issue documenting the
22+
decision).
23+
24+
The email below is calibration — we want to know whether and how
25+
upstream would like a contribution before sinking multi-quarter
26+
effort. It commits the cooperative to no timeline, no scope, and no
27+
delivery.
28+
29+
## How this gets sent
30+
31+
1. Agent 4 drafts (this PR).
32+
2. Agent R reviews the draft like any other PR — same `review-pending`
33+
+ `stream-4` discipline.
34+
3. Marcos reads the merged content, copy-pastes into his mail client,
35+
adapts tone if he wants, sends from `m@pop.coop`.
36+
4. Once Marcos has sent it, Agent 4 updates
37+
`2026-05-05-litepcie-ecp5phy.md` from `scoping`
38+
`awaiting-upstream-feedback` with the send date in a follow-up PR.
39+
5. When Florent replies (or doesn't, after a reasonable interval),
40+
Marcos reports the response and Agent 4 updates the contribution
41+
log to `maintainer-response-{accepted|rejected|deferred}` plus
42+
next-step derivation.
43+
44+
Agent 4 does **not** send mail. Agent 4 does **not** use any
45+
sock-puppet account. Agent 4 does **not** post the email content
46+
anywhere public until after Florent has replied (the contribution log
47+
will summarise the exchange respectfully, not paste the raw email).
48+
49+
## Email draft
50+
51+
---
52+
53+
**From:** Marcos Méndez Quintero `<m@pop.coop>`
54+
**To:** Florent Kermarrec `<florent@enjoy-digital.fr>`
55+
**Subject:** LitePCIe + Lattice ECP5 — scoping question from a small open-hardware cooperative
56+
57+
Hi Florent,
58+
59+
I run **PopSolutions Cooperative** — a small open-hardware project
60+
designing FPGA-based AI inference boards aimed at making model
61+
execution accessible outside the regions that can buy a GPU at sticker
62+
price. Our rev-A board uses a Lattice ECP5-85F with a DDR3-1600
63+
SO-DIMM and an end-to-end open toolchain (yosys + nextpnr-ecp5 +
64+
prjtrellis + LiteDRAM). Public, BSD-style work; not a proprietary
65+
fork trying to commoditise your tooling.
66+
67+
I'm writing to you directly rather than opening a GitHub issue
68+
because (a) the LitePCIe README points to this address for support
69+
discussions, (b) what I have is an architectural question, not a bug
70+
report, and (c) I'd rather calibrate expectations privately before
71+
the cooperative spends real time on a contribution you might not want.
72+
73+
### What we found
74+
75+
While scoping our rev-A host link, we did a one-day audit of LitePCIe:
76+
77+
- `litepcie/phy/` ships PHY modules for Cyclone V, Gowin GW5A, Lattice
78+
CertusPro-NX, and three Xilinx variants. There is no
79+
`ecp5pciephy.py`.
80+
- A search of the LitePCIe issue tracker and PR history for
81+
`lattice OR ecp5` returns zero results — open, closed, or merged.
82+
- The README's "Possible improvements" list includes "add Lattice
83+
support", which is what motivated us to dig further.
84+
- Reading `phy/lfcpnxpciephy.py` end-to-end, we noticed it wraps a
85+
Lattice-generated Verilog IP blob downloaded at build time. That
86+
pattern works for CertusPro-NX because the silicon ships an
87+
integrated PCIe controller. ECP5 is different: it exposes the PCS /
88+
SerDes hard block (DCU) only — the PIPE-to-TLP stack (LTSSM, DLL,
89+
TLP framing, flow-control credits) has to be soft-implemented or
90+
ported. The closed Diamond toolchain has a soft IP for this; we
91+
haven't been able to find a production-mature open equivalent.
92+
93+
That makes a hypothetical `ecp5pciephy.py` substantially more work
94+
than the CertusPro-NX file would suggest at first glance. Our honest
95+
internal estimate is multi-quarter, not multi-sprint.
96+
97+
(Our public scoping notes, in case the file references are useful:
98+
`https://github.com/popsolutions/Stays/blob/main/docs/upstream-contributions/0001-rev-a-known-upstream-issues.md`
99+
— rev-A toolchain survey that surfaced the gap.)
100+
101+
### What I'd like to ask you
102+
103+
No specific commitment expected from this email — these are
104+
calibration questions:
105+
106+
1. **Is our diagnosis correct?** Specifically, that ECP5 has only a
107+
PCS hard block and that any LitePCIe ECP5 PHY would need a soft
108+
PCIe controller stack on top, or alternatively a wrapper around
109+
the closed Diamond IP?
110+
2. **Has the project considered ECP5 support before?** If so, where
111+
did the consideration stop, and what would change to restart it?
112+
3. **What scope of initial PR would you find acceptable?** A bare
113+
PHY-layer module that assumes downstream consumers handle
114+
DLL/TL? A full stack on first PR? Something stacked over multiple
115+
PRs (PHY → DLL → TL across releases)?
116+
4. **Is sponsorship the right channel for work of this scope?** I
117+
noticed `sponsor-welcome` labels on related issues (e.g. #122).
118+
The cooperative has limited funding but takes the question
119+
seriously — if a paid scoping engagement is the right way to start
120+
rather than community-contribution, we'd like to know.
121+
122+
A response of "we don't think this fits LitePCIe upstream" or "we'd
123+
only want this work under a sponsorship contract" or "this is too far
124+
from our priorities to give input on" is equally legitimate and
125+
equally welcome. I'd rather know now than discover it after a PR.
126+
127+
In parallel with this question, our rev-A board is switching its host
128+
link to GbE via LiteEth, so PopSolutions is not blocked on an answer
129+
— this contribution is a forward-looking gift on its own honest
130+
timeline, not a tactical necessity.
131+
132+
Thank you for the time, and for LitePCIe in general — the codebase
133+
read cleanly enough that a one-day external audit could form a
134+
reasonable opinion, which speaks to the project's quality.
135+
136+
Best regards,
137+
Marcos Méndez Quintero
138+
PopSolutions Cooperative
139+
`m@pop.coop`
140+
`https://github.com/popsolutions`
141+
142+
---
143+
144+
## Notes for Marcos before sending
145+
146+
- Replace any phrasing that doesn't sound like you. The above
147+
prioritises calibration over personality; your real voice will read
148+
better than a polished draft.
149+
- Verify the public link in section "Our public scoping notes" still
150+
resolves to the survey doc on `main` at the moment you send (the
151+
doc is on `main` as of 2026-05-05 via PR #3).
152+
- If you want a public artefact later, the contribution-log PR
153+
(popsolutions/Stays#17) is where the response gets summarised,
154+
respectfully and without quoting Florent's reply verbatim unless he
155+
authorises it.
156+
- If you adapt the subject line, keep three signals: ECP5/Lattice,
157+
scoping/exploratory, small-cooperative (so it stands apart from
158+
vendor outreach in his inbox).
159+
160+
Authored by Agent 4 (Open FPGA Upstream Contributions).

0 commit comments

Comments
 (0)