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a62406c
riscv: Add detect_cpu
loganchien Apr 23, 2021
c234c6b
riscv: Add CPU and Assembler scaffold
loganchien Apr 24, 2021
18649b0
riscv: Add code builder
loganchien May 2, 2021
fbcd873
riscv: Compile first loop
loganchien May 16, 2021
092bad3
riscv: Enhance load integer immediate
loganchien May 16, 2021
54afa92
riscv: Support float and compile test_compile_linear_float_loop
loganchien May 16, 2021
d8dfc5c
riscv: Support int_sub
loganchien Jun 17, 2021
cd968b4
riscv: Support int_mul
loganchien Jun 17, 2021
5570c13
riscv: Support int_and/int_or/int_xor
loganchien Jun 17, 2021
4550b1c
riscv: Support int_lshift/int_rshift/uint_rshift
loganchien Jun 17, 2021
577e99a
riscv: Support uint_mul_high
loganchien Jun 17, 2021
90f1b0e
riscv: Add seqz/snez/sltz/sgtz pseudo-instructions
loganchien Jun 18, 2021
345634d
riscv: Support int_lt/int_le/int_eq/int_ne/int_gt/int_ge
loganchien Jun 18, 2021
835437a
riscv: Support uint_lt/uint_le/uint_gt/uint_ge
loganchien Jun 21, 2021
30e49e3
riscv: Add not/neg pseudo-instructions
loganchien Jun 21, 2021
d0f2207
riscv: Support int_is_true/int_neg/int_invert/int_is_zero
loganchien Jun 21, 2021
f925ed3
riscv: Support float_sub/float_mul/float_truediv
loganchien Jun 22, 2021
3d75b2f
riscv: Support float_lt/_le/_gt/_ge/_eq/_ne
loganchien Jun 22, 2021
e5bb632
riscv: Add fneg_d/fabs_d pseudo-instructions
loganchien Jun 22, 2021
1bb5f84
riscv: Support float_neg/float_abs
loganchien Jun 22, 2021
cf77972
riscv: Support cast_int_to_float/cast_float_to_int
loganchien Jun 22, 2021
21a5d49
riscv: Add fmv.d pseudo-instruction
loganchien Sep 25, 2021
eacc243
riscv: Support same_as/cast_int_to_ptr/cast_ptr_to_int
loganchien Sep 25, 2021
539ce58
riscv: Ignore unused operations without side effects
loganchien Sep 25, 2021
baa67e7
riscv: Add beqz/bnez/blez/bgez/bltz/bgtz pseudo-instructions
loganchien Jun 27, 2021
c0b3d35
riscv: Add nop pseudo-instruction
loganchien Jun 27, 2021
12e475d
riscv: Add absolute jump code builder
loganchien Jun 27, 2021
7075711
riscv: Support guard_true/_false/_value/_nonnull/_isnull
loganchien Jun 27, 2021
b6fbc27
riscv: Optimize int-compare-and-branch
loganchien Jan 3, 2022
8187e7e
riscv: Support int_add_ovf/int_sub_ovf/int_mul_ovf
loganchien Jul 21, 2022
50a635a
riscv: Support force_spill
loganchien Jul 21, 2022
da85e1b
riscv: Support int_signext
loganchien Jul 21, 2022
20fbf0f
riscv: Support int_force_ge_zero
loganchien Jul 23, 2022
cf8bb8a
riscv: Reserve f31 as a scratch fp register
loganchien Dec 27, 2022
33b4ad8
riscv: Add ConstFloatImm support to regalloc_mov
loganchien Dec 28, 2022
d2f7e06
riscv: Add regalloc_push/pop/prepare_move utilities
loganchien Dec 28, 2022
63563ae
riscv: Support label/jump
loganchien Dec 29, 2022
8867cec
riscv: Support call op
loganchien Oct 19, 2023
bf10943
riscv: Support fast sqrt
loganchien Oct 19, 2023
defbcb2
riscv: Support cond_call
loganchien Nov 22, 2023
e5e875e
riscv: Support guard_op_cond_call_op
loganchien Nov 29, 2023
9eca3b9
riscv: Add FENCE/LR/SC/AMO code builder
loganchien Dec 6, 2023
18e58dc
riscv: Support call_release_gil
loganchien Dec 22, 2023
3ec20c8
riscv: Support call_release_gil with save errno
loganchien Dec 22, 2023
794366d
riscv: Add missing push_gcmap to op_finish
loganchien Jan 2, 2024
5283c11
riscv: Support force_token/guard_not_forced_2
loganchien Dec 23, 2023
3e02f38
riscv: Support call_may_force
loganchien Dec 23, 2023
83fb732
riscv: Change cond_call_slowpath to use x30
loganchien Dec 24, 2023
4fa86db
riscv: Support cond_call_gc_wb/_array
loganchien Dec 25, 2023
4101d4c
riscv: Support bitcast conversion between float/longlong
loganchien Dec 25, 2023
8c5408a
riscv: Support gc_load/store and gc_indexed_load/store
loganchien Dec 25, 2023
fef6e95
riscv: Add ConstPtr support to return_constant
loganchien Dec 26, 2023
8c8bdd8
riscv: Support exceptions
loganchien Dec 26, 2023
7cfce35
riscv: Support check_memory_error
loganchien Dec 26, 2023
7f6e6cf
riscv: Support ptr_eq/ptr_ne
loganchien Dec 26, 2023
c374b6d
riscv: Support guard_class/guard_nonnull_class
loganchien Dec 26, 2023
be9baf3
riscv: Support compile_bridge
loganchien Dec 27, 2023
dd0cb70
riscv: Support guard_not_invalidated
loganchien Dec 27, 2023
d69b0c3
riscv: Support call_assembler
loganchien Dec 28, 2023
7e019a1
riscv: Support redirect_call_assembler
loganchien Dec 28, 2023
293d379
riscv: Add passing test_calling_convention
loganchien Jan 16, 2024
44d53ce
riscv: Fix test_compile_asmlen
loganchien Dec 28, 2023
679bdde
riscv: Support jit_debug and increment_debug_counter
loganchien Dec 28, 2023
fe978a0
riscv: Support zero_array
loganchien Dec 28, 2023
9f0d3ec
riscv: Support enter_portal_frame/leave_portal_frame
loganchien Dec 29, 2023
2d73d9f
riscv: Support keepalive
loganchien Jan 1, 2024
6583668
riscv: Add several passing ajit tests
loganchien Jan 2, 2024
df14a36
riscv: Add passing test_zrpy_gc_boehm
loganchien Jan 2, 2024
3cfe27c
riscv: Add stack overflow check
loganchien Jan 4, 2024
f629fd9
riscv: Add threadlocalref_get
loganchien Jan 6, 2024
d36378f
riscv: Add shadow stack to header/footer
loganchien Jan 6, 2024
2fda659
riscv: Add guard_gc_type/guard_subclass/guard_is_object
loganchien Jan 7, 2024
7daf0e4
riscv: Support call_malloc_nursery/nursery_ptr_increment
loganchien Jan 2, 2024
8245888
riscv: Add passing test_zrpy_gc
loganchien Jan 8, 2024
329d2eb
riscv: Add passing test_zrpy_releasegil
loganchien Jan 9, 2024
1b2e214
riscv: Add passing test_ztranslation* tests
loganchien Jan 12, 2024
598c03a
riscv: Add slp_switch implementation for rv64imad
loganchien Jan 13, 2024
4fd0116
riscv: Add codemap support
loganchien Jan 14, 2024
78276e3
riscv: Support vmprof
loganchien Jan 15, 2024
c51e30d
riscv: Emit large int or float in constant pool
loganchien Jan 21, 2024
f0953f2
riscv: Support large frame slot offsets
loganchien Jan 28, 2024
0567179
riscv: Add cross-translation doc
loganchien Jan 16, 2024
47cf262
riscv: Skip micronumpy tests w/ nan payloads
loganchien Feb 10, 2024
ac2cd0d
riscv: Fix test_gc_integration
loganchien Feb 19, 2024
780ec9e
riscv: Fix vtable offset assertion
loganchien Feb 20, 2024
cafff50
riscv: Annotate rgc.no_release_gil
loganchien Feb 24, 2024
b4a065b
riscv: Swap order of x0 and x10 in JITFRAME
loganchien Feb 12, 2024
cb83034
riscv: Workaround test_micronumpy reduce_logical_and
loganchien Aug 7, 2024
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22 changes: 21 additions & 1 deletion pypy/module/micronumpy/test/test_ndarray.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
# -*- encoding: utf-8 -*-
import platform
import py
import sys

Expand Down Expand Up @@ -1879,12 +1880,18 @@ def test_array_view(self):
assert a.view('S16')[0] == '\x01' + '\x00' * 7 + '\x02'

def test_half_conversions(self):
from numpy import array, arange
from numpy import array
from math import isnan, isinf
e = array([0, -1, -float('inf'), float('nan'), 6], dtype='float16')
assert map(isnan, e) == [False, False, False, True, False]
assert map(isinf, e) == [False, False, True, False, False]
assert e.argmax() == 3

def test_half_conversions_preserve_nan_payload_float32(self):
if platform.machine().startswith('riscv'):
py.test.skip('riscv does not preserve nan payload in '
'float64->float32 conversion')
from numpy import array, arange
# numpy preserves value for uint16 -> cast_as_float16 ->
# convert_to_float64 -> convert_to_float16 -> uint16
# even for float16 various float16 nans
Expand All @@ -1896,6 +1903,19 @@ def test_half_conversions(self):
d = all_f16.view(dtype='uint16')
assert (c == d).all()

def test_half_conversions_preserve_nan_payload_float64(self):
from numpy import array, arange
# numpy preserves value for uint16 -> cast_as_float16 ->
# convert_to_float64 -> convert_to_float16 -> uint16
# even for float16 various float16 nans
all_f16 = arange(0xfe00, 0xffff, dtype='uint16')
all_f16.dtype = 'float16'
all_f64 = array(all_f16, dtype='float64')
b = array(all_f64, dtype='float16')
c = b.view(dtype='uint16')
d = all_f16.view(dtype='uint16')
assert (c == d).all()

def test_ndarray_view_empty(self):
from numpy import array, dtype
x = array([], dtype=[('a', 'int8'), ('b', 'int8')])
Expand Down
14 changes: 14 additions & 0 deletions pypy/module/micronumpy/test/test_ufuncs.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
import platform
import py

from pypy.module.micronumpy.test.test_base import BaseNumpyAppTest
from pypy.module.micronumpy.ufuncs import W_UfuncGeneric, unary_ufunc
from pypy.module.micronumpy.support import _parse_signature
Expand Down Expand Up @@ -808,8 +811,19 @@ def test_floorceiltrunc(self):
assert ([ninf, -2.0, -2.0, -1.0, 0.0, 1.0, 1.0, 0.0, inf] == floor(a)).all()
assert ([ninf, -1.0, -1.0, -1.0, 0.0, 1.0, 2.0, 1.0, inf] == ceil(a)).all()
assert ([ninf, -1.0, -1.0, -1.0, 0.0, 1.0, 1.0, 0.0, inf] == trunc(a)).all()

def test_floorceiltrunc_nan(self):
from numpy import floor, ceil, trunc
import math
assert all([math.isnan(f(float("nan"))) for f in floor, ceil, trunc])
assert all([math.copysign(1, f(abs(float("nan")))) == 1 for f in floor, ceil, trunc])

def test_floorceiltrunc_nan_negative(self):
if platform.machine().startswith('riscv'):
py.test.skip('riscv floor/ceil/trunc canonicalizes nan to '
'positive nan')
from numpy import floor, ceil, trunc
import math
assert all([math.copysign(1, f(-abs(float("nan")))) == -1 for f in floor, ceil, trunc])

def test_round(self):
Expand Down
41 changes: 29 additions & 12 deletions pypy/module/pypyjit/test_pypy_c/test_micronumpy.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

IS_X86 = platform.machine().startswith('x86') or platform.machine() == 'i686'
IS_S390X = platform.machine() == "s390x"
IS_RISCV = platform.machine() == 'riscv64'

def no_vector_backend():
if IS_X86:
Expand Down Expand Up @@ -206,18 +207,34 @@ def main():
assert log.result is True
assert len(log.loops) == 1
loop = log._filter(log.loops[0])
loop.match("""
%(align_check)s
guard_not_invalidated(descr=...)
f31 = raw_load_f(i9, i29, descr=<ArrayF 8>)
i32 = float_ne(f31, 0.000000)
guard_true(i32, descr=...)
i36 = int_add(i24, 1)
i37 = int_add(i29, 8)
i38 = int_ge(i36, i30)
guard_false(i38, descr=...)
jump(..., descr=...)
""" % {'align_check': align_check('i29')})
if IS_RISCV:
# The order of %(align_check)s and guard_not_invalidated(descr=...)
# in the RISCV backend is different from other backends.
loop.match("""
guard_not_invalidated(descr=...)
%(align_check)s
f31 = raw_load_f(i9, i29, descr=<ArrayF 8>)
i32 = float_ne(f31, 0.000000)
guard_true(i32, descr=...)
i36 = int_add(i24, 1)
i37 = int_add(i29, 8)
i38 = int_ge(i36, i30)
guard_false(i38, descr=...)
jump(..., descr=...)
""" % {'align_check': align_check('i29')})
else:
loop.match("""
%(align_check)s
guard_not_invalidated(descr=...)
f31 = raw_load_f(i9, i29, descr=<ArrayF 8>)
i32 = float_ne(f31, 0.000000)
guard_true(i32, descr=...)
i36 = int_add(i24, 1)
i37 = int_add(i29, 8)
i38 = int_ge(i36, i30)
guard_false(i38, descr=...)
jump(..., descr=...)
""" % {'align_check': align_check('i29')})
# vector version
#assert loop.match("""
# guard_not_invalidated(descr=...)
Expand Down
1 change: 1 addition & 0 deletions rpython/doc/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ RPython.
:maxdepth: 1

arm
riscv
logging


Expand Down
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