Upstream cpuinfo updates in XNNPACK as of XNNPACK Git revision c58bd34

CMakeLists.txt

@@ -179,7 +179,6 @@ IF(CPUINFO_SUPPORTED_PLATFORM)
     LIST(APPEND CPUINFO_SRCS
       src/linux/smallfile.c
       src/linux/multiline.c
-      src/linux/current.c
       src/linux/cpulist.c
       src/linux/processors.c)
   ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "Darwin" OR CMAKE_SYSTEM_NAME STREQUAL "iOS")

README.md

@@ -152,21 +152,20 @@ pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpu_set);
   - [x] Using `ro.chipname`, `ro.board.platform`, `ro.product.board`, `ro.mediatek.platform`, `ro.arch` properties (Android)
   - [ ] Using kernel log (`dmesg`) on ARM Linux
 - Vendor and microarchitecture detection
-  - [x] Intel-designed x86/x86-64 cores (up to Kaby Lake, Airmont, and Knights Mill)
-  - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen)
+  - [x] Intel-designed x86/x86-64 cores (up to Sunny Cove, Goldmont Plus, and Knights Mill)
+  - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen 2)
   - [ ] VIA-designed x86/x86-64 cores
   - [ ] Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise)
-  - [x] ARM-designed ARM cores (up to Cortex-A55 and Cortex-A75)
-  - [x] Qualcomm-designed ARM cores (up to Kryo, Kryo-280, and Kryo-385)
-  - [x] Nvidia-designed ARM cores (Denver)
+  - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/N1)
+  - [x] Qualcomm-designed ARM cores (Scorpion, Krait, and Kryo)
+  - [x] Nvidia-designed ARM cores (Denver and Carmel)
   - [x] Samsung-designed ARM cores (Exynos)
   - [x] Intel-designed ARM cores (XScale up to 3rd-gen)
-  - [x] Apple-designed ARM cores (up to Hurricane)
+  - [x] Apple-designed ARM cores (up to Lightning and Thunder)
   - [x] Cavium-designed ARM cores (ThunderX)
   - [x] AppliedMicro-designed ARM cores (X-Gene)
 - Instruction set detection
   - [x] Using CPUID (x86/x86-64)
-  - [x] Using dynamic code generation validator (Native Client/x86-64)
   - [x] Using `/proc/cpuinfo` on 32-bit ARM EABI (Linux)
   - [x] Using microarchitecture heuristics on (32-bit ARM)
   - [x] Using `FPSID` and `WCID` registers (32-bit ARM)

bench/get-current.cc

@@ -21,4 +21,13 @@ static void cpuinfo_get_current_core(benchmark::State& state) {
 }
 BENCHMARK(cpuinfo_get_current_core)->Unit(benchmark::kNanosecond);
 
+static void cpuinfo_get_current_uarch_index(benchmark::State& state) {
+	cpuinfo_initialize();
+	while (state.KeepRunning()) {
+		const uint32_t uarch_index = cpuinfo_get_current_uarch_index();
+		benchmark::DoNotOptimize(uarch_index);
+	}
+}
+BENCHMARK(cpuinfo_get_current_uarch_index)->Unit(benchmark::kNanosecond);
+
 BENCHMARK_MAIN();

cmake/DownloadGoogleTest.cmake

@@ -4,8 +4,8 @@ PROJECT(googletest-download NONE)
 
 INCLUDE(ExternalProject)
 ExternalProject_Add(googletest
-	URL https://github.com/google/googletest/archive/release-1.8.0.zip
-	URL_HASH SHA256=f3ed3b58511efd272eb074a3a6d6fb79d7c2e6a0e374323d1e6bcbcc1ef141bf
+	URL https://github.com/google/googletest/archive/release-1.10.0.zip
+	URL_HASH SHA256=94c634d499558a76fa649edb13721dce6e98fb1e7018dfaeba3cd7a083945e91
 	SOURCE_DIR "${CONFU_DEPENDENCIES_SOURCE_DIR}/googletest"
 	BINARY_DIR "${CONFU_DEPENDENCIES_BINARY_DIR}/googletest"
 	CONFIGURE_COMMAND ""

configure.py

@@ -26,8 +26,8 @@ def main(args):
         sources = ["init.c", "api.c"]
         if build.target.is_x86 or build.target.is_x86_64:
             sources += [
-                "x86/init.c", "x86/info.c", "x86/vendor.c", "x86/uarch.c", "x86/name.c",
-                "x86/topology.c",
+                "x86/init.c", "x86/info.c", "x86/isa.c", "x86/vendor.c",
+                "x86/uarch.c", "x86/name.c", "x86/topology.c",
                 "x86/cache/init.c", "x86/cache/descriptor.c", "x86/cache/deterministic.c",
             ]
             if build.target.is_macos:
@@ -37,7 +37,6 @@ def main(args):
                     "x86/linux/init.c",
                     "x86/linux/cpuinfo.c",
                 ]
-            sources.append("x86/isa.c" if not build.target.is_nacl else "x86/nacl/isa.c")
         if build.target.is_arm or build.target.is_arm64:
             sources += ["arm/uarch.c", "arm/cache.c"]
             if build.target.is_linux or build.target.is_android:

include/cpuinfo.h

@@ -34,10 +34,6 @@
 	#define CPUINFO_ARCH_PPC64 1
 #endif
 
-#if defined(__pnacl__)
-	#define CPUINFO_ARCH_PNACL 1
-#endif
-
 #if defined(__asmjs__)
 	#define CPUINFO_ARCH_ASMJS 1
 #endif
@@ -80,10 +76,6 @@
 	#define CPUINFO_ARCH_PPC64 0
 #endif
 
-#ifndef CPUINFO_ARCH_PNACL
-	#define CPUINFO_ARCH_PNACL 0
-#endif
-
 #ifndef CPUINFO_ARCH_ASMJS
 	#define CPUINFO_ARCH_ASMJS 0
 #endif
@@ -190,6 +182,12 @@ enum cpuinfo_vendor {
 	 * Processors are designed by HiSilicon, a subsidiary of Huawei.
 	 */
 	cpuinfo_vendor_huawei   = 15,
+	/**
+	 * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor of x86-64 processor microarchitectures.
+	 *
+	 * Processors are variants of AMD cores.
+	 */
+	cpuinfo_vendor_hygon    = 16,
 
 	/* Active vendors of embedded CPUs */
 
@@ -401,6 +399,8 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_cortex_a35   = 0x00300335,
 	/** ARM Cortex-A53. */
 	cpuinfo_uarch_cortex_a53   = 0x00300353,
+	/** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+). */
+	cpuinfo_uarch_cortex_a55r0 = 0x00300354,
 	/** ARM Cortex-A55. */
 	cpuinfo_uarch_cortex_a55   = 0x00300355,
 	/** ARM Cortex-A57. */
@@ -478,6 +478,10 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_vortex    = 0x00700107,
 	/** Apple A12 processor (little cores). */
 	cpuinfo_uarch_tempest   = 0x00700108,
+	/** Apple A13 processor (big cores). */
+	cpuinfo_uarch_lightning = 0x00700109,
+	/** Apple A13 processor (little cores). */
+	cpuinfo_uarch_thunder   = 0x0070010A,
 
 	/** Cavium ThunderX. */
 	cpuinfo_uarch_thunderx = 0x00800100,
@@ -494,6 +498,9 @@ enum cpuinfo_uarch {
 
 	/** Applied Micro X-Gene. */
 	cpuinfo_uarch_xgene = 0x00B00100,
+
+	/* Hygon Dhyana (a modification of AMD Zen for Chinese market). */
+	cpuinfo_uarch_dhyana = 0x01000100,
 };
 
 struct cpuinfo_processor {
@@ -613,6 +620,22 @@ struct cpuinfo_package {
 	uint32_t cluster_count;
 };
 
+struct cpuinfo_uarch_info {
+	/** Type of CPU microarchitecture */
+	enum cpuinfo_uarch uarch;
+#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
+	/** Value of CPUID leaf 1 EAX register for the microarchitecture */
+	uint32_t cpuid;
+#elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
+	/** Value of Main ID Register (MIDR) for the microarchitecture */
+	uint32_t midr;
+#endif
+	/** Number of logical processors with the microarchitecture */
+	uint32_t processor_count;
+	/** Number of cores with the microarchitecture */
+	uint32_t core_count;
+};
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -1721,6 +1744,7 @@ const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void);
 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_cores(void);
 const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_clusters(void);
 const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_packages(void);
+const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarchs(void);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void);
@@ -1731,6 +1755,7 @@ const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processor(uint32_t index
 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_core(uint32_t index);
 const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_cluster(uint32_t index);
 const struct cpuinfo_package* CPUINFO_ABI cpuinfo_get_package(uint32_t index);
+const struct cpuinfo_uarch_info* CPUINFO_ABI cpuinfo_get_uarch(uint32_t index);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index);
 const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index);
@@ -1741,6 +1766,7 @@ uint32_t CPUINFO_ABI cpuinfo_get_processors_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_cores_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_clusters_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_packages_count(void);
+uint32_t CPUINFO_ABI cpuinfo_get_uarchs_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void);
 uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void);
@@ -1752,9 +1778,31 @@ uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void);
  */
 uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void);
 
+/**
+ * Identify the logical processor that executes the current thread.
+ *
+ * There is no guarantee that the thread will stay on the same logical processor for any time.
+ * Callers should treat the result as only a hint, and be prepared to handle NULL return value.
+ */
 const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void);
+
+/**
+ * Identify the core that executes the current thread.
+ *
+ * There is no guarantee that the thread will stay on the same core for any time.
+ * Callers should treat the result as only a hint, and be prepared to handle NULL return value.
+ */
 const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void);
 
+/**
+ * Identify the microarchitecture index of the core that executes the current thread.
+ * If the system does not support such identification, the function return 0.
+ *
+ * There is no guarantee that the thread will stay on the same type of core for any time.
+ * Callers should treat the result as only a hint.
+ */
+uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void);
+
 #ifdef __cplusplus
 } /* extern "C" */
 #endif