Preserve port order in module instantiation #839
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Updates for leonardt/verilogAST-cpp#39 so that the order of ports for module instances are preserved. The old logic used a std::map which uses lexical order, causing the output to sort the ports based on the names. Migrating to a std::vector preserve's CoreIR's internal ordering of the ports (which is based on insertion order)
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See leonardt/verilogAST-cpp#39. I think this is a good change but we should lock it into the spec, so that the generated verilog doesn't keep changing. |
rsetaluri
approved these changes
Feb 13, 2020
This was referenced Feb 21, 2020
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Updates for leonardt/verilogAST-cpp#39 so that
the order of ports for module instances are preserved. The old logic
used a std::map which uses lexical order, causing the output to sort
the ports based on the names. Migrating to a std::vector preserve's
CoreIR's internal ordering of the ports (which is based on insertion
order)