Replies: 8 comments 6 replies
-
|
This is very useful information, thank you for sharing! I only drew enough schematics to get me to a useful memory map and decide that the serial port logic was weird and I didn't need to figure it out. At least they're started and can be built on if needed! If anyone is willing to send me failed boards I would be more than happy to give them this treatment for easy schematic reverse engineering. As it is, I have only the one unit and cannot do anything destructive. |
Beta Was this translation helpful? Give feedback.
-
|
There is 8x analog mux (4051B) next to the servo connector. This switches different resistor dividers. It is controlled by label 119 called "AD offset voltage". The output of the mux goes to first pin of 18pin connector (cable goes to other side of station) Control input is from MC14504 hex ttl to cmos converter. Controlled by addresses in EXTRAM space 0x13, 0x14, 0x15 (need to confirm) |
Beta Was this translation helpful? Give feedback.
-
|
Here is pinout of connectors that i have so far. Strange thing is: There are multiple RS232 serial ports - radio, 2ports from CU, and 2 rs232 ports on mainboard. MAX232 on PVX board is used for "tribrach" connector and for radio. I have no idea how the switching to other ports is done. My guess is that when station recognizes there is CU on station, it puts CU in between "tribrach" connector and station. But i dont know how that is acomplished. EXTRAM 0x16-0x1A addresses are involved. Radio has special feature (from 4400 station notes): it can tell PSU to power on the station, there is one line from radio to station, i guess this is it. White and brown are .... white and brown cables that go to angle sensors and plumb. This is the excitation signal for the sensors. (there is oscillator and transformer on the angle sensor board. (this was separate board on 4400 station) The board that connects to CU has additional connector, I think this one is for "dual sided" cu port. Power to angle sensor goes through 6pin board to the circular board in middle of station. And i have absolutely no idea what 10pin connector is used for. It might be used in different configuration of station. There is just the A/M switch connected on mine. |
Beta Was this translation helpful? Give feedback.
-
|
|
Beta Was this translation helpful? Give feedback.
-
Beta Was this translation helpful? Give feedback.
-
|
EXTRAM and CODE section is the same memory, EXCEPT for 0x0000 - 0x2000 (bootrom) or 0x0000-0x4000 (with larger bootrom, i dont have such chip, so i will talk about the first one) That means ... memory from 0x2000 can be accessed both using EXTRAM (movx) and CODE (movc) instructions, its RW access (in case of EXTRAM and enabled writes) In both cases it accesses external ram |
Beta Was this translation helpful? Give feedback.
-
|
internal memory and registers: registers are part of internal memory. |
Beta Was this translation helpful? Give feedback.
-
Beta Was this translation helpful? Give feedback.
-
|
When i say RAM i refer to External RAM. I don't care about internal ram, its mainly used for register banks and stack. |
Beta Was this translation helpful? Give feedback.
-
|
First the following links have been very useful in answering a lot of questions about the quirks of 8051: https://www.electronicshub.org/8051-microcontroller-introduction/ (along with datasheets of course) In the pin diagram document (4th link above) it states the following: Pin 29 (PSEN): Pin 29 is the Program Store Enable Pin (PSEN). Using this pins, external Program Memory can be read. On the 40 pin DIP... On the 44PLCC package PSEN is pin 32: I have designed and soldered computers based on microprocessors, meaning I have designed chip select circuitry. My Harvard Architecture projects always used only internal program and data memory, (single chip computers / microcontrollers). It seems to me for a Harvard Architecture processor like the 8051, for the Battery-Backed-External RAM to be accessable as both program memory and data memory (MOVC and MOVX), then Pin 32 is simply not connected. Is this accurate? That way regardless of what the processor is signalling on PSEN it is always accessing the same memory chip for both program and data memory, changing it back to a Von Neumann Architecture. |
Beta Was this translation helpful? Give feedback.
-
|
As a cool side effect, I have noticed in third link above on memory organization, they show how to disable internal program memory and use only external program memory, by wiring the EA (active low) to GND. It means one can make their own bootrom code for the GDM, and load it into the bottom 8k of the 32K Battery-Backed-RAM and (powering down first) at the flick of a switch move back and forth between using the original and home brew bootloader. The reason I mention this is, the bootrom appears to have 1.5k of free space for more code (only 81% used). After developing and thoroughly testing a homebrew bootrom image, one might program the image into a different P87C51FA chip (in the 600 series GDMs) and flick the switch back to accessing the internal bootrom, then one might use the code space at the image of the Battery-Backed-RAM at $8000 which would otherwise mirror at $0000. |
Beta Was this translation helpful? Give feedback.
-
|
could you please keep your comments to single thread ? :) |
Beta Was this translation helpful? Give feedback.
-
|
OK |
Beta Was this translation helpful? Give feedback.
-
|
I believe, too, that this discussion should stay limited to the hardware schematics and pinouts. Probably best to start a disassembly specific discussion, @MattMalone . The schematics I published here should have the full memory select decoding and I believe processor boot config strapping shown. It has been an while but I think I did that. |
Beta Was this translation helpful? Give feedback.
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
-
@bdm310 I have seen your schematics, i thought you have drawn them fully. That would be crazy :)
Main board is called PVX. The latest one is PVX 4 or something like that, and it does not contain the discrete logic anymore. There is fpga to do this.
memory map:
Banks are controlled by P1.4, P3.0, P3.1 or P1.4. P3.4, P3.5 depends on hw version of pvx (i thing its the discrete logic vs fpga)
Serial ports:
there is some kind of magical switch on the serial ports. Controlled by SC2692 OP7. (if you plug in CU to station, base serial port goes to CU)
MCU pinout
POA - angle board, EDM - distance meter, SRV servo
SCC2692 has 8 outputs and 8 inputs.
Beta Was this translation helpful? Give feedback.
All reactions