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Vincent merge #4

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92b24ac
Clean directory for clock_divider
vfcheung Feb 28, 2019
e116ee7
Fix merge conflict
vfcheung Feb 28, 2019
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84 changes: 2 additions & 82 deletions CS152A_lab4.gise
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Original file line number Diff line number Diff line change
Expand Up @@ -21,88 +21,8 @@

<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="CS152A_lab4.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="clock_divider_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="clock_divider_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="clock_divider_tb_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<files xmlns="http://www.xilinx.com/XMLSchema"/>

<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1551381765" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1551381765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551381949" xil_pn:in_ck="-2291216993699917254" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1551381949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="clock_divider.v"/>
<outfile xil_pn:name="clock_divider_tb.v"/>
<outfile xil_pn:name="debouncer.v"/>
<outfile xil_pn:name="reader.v"/>
<outfile xil_pn:name="seven_segment.v"/>
<outfile xil_pn:name="top_lvl_player.v"/>
</transform>
<transform xil_pn:end_ts="1551381765" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6399732072652869950" xil_pn:start_ts="1551381765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551381765" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3468867671562984196" xil_pn:start_ts="1551381765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551381765" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8552113841607521573" xil_pn:start_ts="1551381765">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1551381950" xil_pn:in_ck="-2291216993699917254" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1551381949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="clock_divider.v"/>
<outfile xil_pn:name="clock_divider_tb.v"/>
<outfile xil_pn:name="debouncer.v"/>
<outfile xil_pn:name="reader.v"/>
<outfile xil_pn:name="seven_segment.v"/>
<outfile xil_pn:name="top_lvl_player.v"/>
</transform>
<transform xil_pn:end_ts="1551381952" xil_pn:in_ck="-2291216993699917254" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2873826278212114469" xil_pn:start_ts="1551381950">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="clock_divider_tb_beh.prj"/>
<outfile xil_pn:name="clock_divider_tb_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1551381953" xil_pn:in_ck="-1823959034427665194" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5118077578104439490" xil_pn:start_ts="1551381952">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="clock_divider_tb_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
</transforms>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>

</generated_project>
1 change: 1 addition & 0 deletions CS152A_lab4.xise
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Expand Up @@ -334,6 +334,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
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15 changes: 0 additions & 15 deletions _xmsgs/pn_parser.xmsgs
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3 changes: 0 additions & 3 deletions clock_divider_tb_beh.prj
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Binary file removed clock_divider_tb_isim_beh.exe
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Binary file removed clock_divider_tb_isim_beh.wdb
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79 changes: 0 additions & 79 deletions debouncer_summary.html
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21 changes: 0 additions & 21 deletions fuse.log
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