Feature-gate csr instructions

riscv-rt/CHANGELOG.md

@@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- New `no-mhartid` feature to load 0 to `a0` instead of reading `mhartid`.
+- New `no-xtvec` feature that removes interrupt stuff.
+
 ### Changed
 
 - Update license to `MIT or Apache-2.0`
@@ -23,7 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - New `post-init` feature to run a Rust `__post_init` function before jumping to `main`.
-- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. 
+- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function.
 - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the
   linker will place this new section in `REGION_BSS`.
 - Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3)
@@ -78,7 +83,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New `device` feature to include `device.x` in `link.x`. This feature is based
   on the current implementation of `cortex-m-rt`.
 - New `memory` feature to include `memory.x` in `link.x`. This feature is based
-  on the current implementation of `cortex-m-rt`. However, in contrast with 
+  on the current implementation of `cortex-m-rt`. However, in contrast with
   `cortex-m-rt`, including `memory.x` in the linker file is feature gated.
   The benefits of leaving this optional are backwards compatibility and
   allowing users to define less typical linker scripts that do not rely on a

riscv-rt/Cargo.toml

@@ -42,7 +42,9 @@ v-trap = ["riscv-rt-macros/v-trap", "riscv/rt-v-trap"]
 u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
 no-interrupts = []
 no-exceptions = []
+no-mhartid = ["single-hart"]
 no-xie-xip = []
+no-xtvec = []
 device = []
 memory = []
 defmt = ["dep:defmt"]

riscv-rt/src/asm.rs

@@ -68,17 +68,26 @@ _abs_start:
     #[cfg(all(feature = "s-mode", not(feature = "no-xie-xip")))]
     "csrw sie, 0
     csrw sip, 0",
-    #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))]
-    "csrw mie, 0
-    csrw mip, 0",
     #[cfg(not(feature = "s-mode"))]
-    "csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
+    {
+        #[cfg(not(feature = "no-xie-xip"))]
+        "csrw mie, 0
+        csrw mip, 0",
+        // Make sure that the hart ID is in a0 in M-mode
+        #[cfg(not(feature = "no-mhartid"))]
+        "csrr a0, mhartid",
+        #[cfg(feature = "no-mhartid")]
+        "li a0, 0",
+    }
     // Set pre-init trap vector
-    "la t0, _pre_init_trap",
-    #[cfg(feature = "s-mode")]
-    "csrw stvec, t0",
-    #[cfg(not(feature = "s-mode"))]
-    "csrw mtvec, t0",
+    #[cfg(not(feature = "no-xtvec"))]
+    {
+        "la t0, _pre_init_trap",
+        #[cfg(feature = "s-mode")]
+        "csrw stvec, t0",
+        #[cfg(not(feature = "s-mode"))]
+        "csrw mtvec, t0",
+    }
     // If multi-hart, assert that hart ID is valid
     #[cfg(not(feature = "single-hart"))]
     "lui t0, %hi(_max_hart_id)

riscv-rt/src/lib.rs

@@ -565,6 +565,15 @@
 //!
 //! Saves a little code size if there is only one hart on the target.
 //!
+//! ## `no-mhartid`
+//!
+//! Skips reading `mhartid` and uses 0 instead. Useful for targets that doesn't implement this instruction.
+//! Automatically enables `single-hart`.
+//!
+//! ## `no-xtvec`
+//!
+//! Skips interrupts setup.
+//!
 //! ## `s-mode`
 //!
 //! Supervisor mode. While most registers/instructions have variants for both `mcause` and
@@ -729,9 +738,9 @@ pub unsafe extern "Rust" fn setup_interrupts() {
 
     let xtvec_val = match () {
         #[cfg(not(feature = "v-trap"))]
-        _ => Xtvec::new(_start_trap as usize, TrapMode::Direct),
+        _ => Xtvec::new(_start_trap as *const () as usize, TrapMode::Direct),
         #[cfg(feature = "v-trap")]
-        _ => Xtvec::new(_vector_table as usize, TrapMode::Vectored),
+        _ => Xtvec::new(_vector_table as *const () as usize, TrapMode::Vectored),
     };
     xtvec::write(xtvec_val);
 }