Additional pthread functions for DragonFly. #251
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These are needed in order to fix/implement the guard page code of Rust for DragonFly.
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@dhuseby: This probably applies to FreeBSD as well. |
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(rust_highfive has picked a reviewer for you, use r? to override) |
| -> ::c_int; | ||
| pub fn clock_gettime(clk_id: ::c_ulong, tp: *mut ::timespec) -> ::c_int; | ||
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| pub fn pthread_attr_get_np(tid: ::pthread_t, |
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do these functions have the same signature on both dragonflybsd and freebsd? if they do, then please put them in the src/unix/bsd/freebsdlike/mod.rs file instead. thanks!
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yes. https://www.freebsd.org/cgi/man.cgi?query=pthread_attr_get_np. Also, guard page code for FreeBSD seems to be missing in Rust. Did you run "gmake check" when building rust? One test that overflows the stack on purpose should also fail for FreeBSD (it fails on DragonFly). I will add those functions then to the common code base for both DragonFly and FreeBSD
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@alexcrichton : I will come up with a patch that also includes support for FreeBSD. Closing this pull request. |
danielverkamp
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Apr 28, 2020
This commit adds a new crate for testing that the intrinsics listed in this crate do indeed match the upstream definition of each intrinsic. A pre-downloaded XML description of all Intel intrinsics is checked in which is then parsed in the `stdsimd-verify` crate to verify that everything we write down is matched against the upstream definitions. Currently the checks are pretty loose to get this compiling but a few intrinsics were fixed as a result of this. For example: * `_mm256_extract_epi8` - AVX2 intrinsic erroneously listed under AVX * `_mm256_extract_epi16` - AVX2 intrinsic erroneously listed under AVX * `_mm256_extract_epi32` - AVX2 intrinsic erroneously listed under AVX * `_mm256_extract_epi64` - AVX2 intrinsic erroneously listed under AVX * `_mm_tzcnt_32` - erroneously had `u32` in the name * `_mm_tzcnt_64` - erroneously had `u64` in the name * `_mm_cvtsi64_si128` - erroneously available on 32-bit platforms * `_mm_cvtsi64x_si128` - erroneously available on 32-bit platforms * `_mm_cvtsi128_si64` - erroneously available on 32-bit platforms * `_mm_cvtsi128_si64x` - erroneously available on 32-bit platforms * `_mm_extract_epi64` - erroneously available on 32-bit platforms * `_mm_insert_epi64` - erroneously available on 32-bit platforms * `_mm256_extract_epi16` - erroneously returned i32 instead of i16 * `_mm256_extract_epi8` - erroneously returned i32 instead of i8 * `_mm_shuffle_ps` - the mask argument was erroneously i32 instead of u32 * `_popcnt32` - the signededness of the argument and return were flipped * `_popcnt64` - the signededness of the argument was flipped and the argument was too large bit-wise * `_mm_tzcnt_32` - the return value's sign was flipped * `_mm_tzcnt_64` - the return value's sign was flipped * A good number of intrinsics used `imm8: i8` or `imm8: u8` instead of `imm8: i32` which Intel was using. (we were also internally inconsistent) * A number of intrinsics working with `__m64` were instead working with i64/u64, so they're now corrected to operate with the vector types instead. Currently the verifications performed are: * Each name in Rust is defined in the XML document * The arguments/return values all agree. * The CPUID features listed in the XML document are all enabled in Rust as well. The type matching right now is pretty loose and has a lot of questionable changes. Future commits will touch these up to be more strict and require closer adherence with Intel's own types. Otherwise types like `i32x8` (or any integers with 256 bits) all match up to `__m256i` right now, althoguh this may want to change in the future. Finally we're also not testing the instruction listed in the XML right now. There's a huge number of discrepancies between the instruction listed in the XML and the instruction listed in `assert_instr`, and those'll need to be taken care of in a future commit. Closes rust-lang#240
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These are needed in order to fix/implement the guard page code of Rust
for DragonFly.