Update the arm-* and aarch64-* platform docs. #146419
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| # `aarch64-unknown-none` and `aarch64-unknown-none-softfloat` | ||
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| * **Tier: 2** | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
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| Bare-metal targets for CPUs in the Armv8-A architecture family, running in AArch64 mode. | ||
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| For the AArch32 mode carried over from Armv7-A, see | ||
| [`armv7a-none-eabi`](armv7a-none-eabi.md) instead. | ||
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| Processors in this family include the [Arm Cortex-A35, 53, 76, etc][aarch64-cpus]. | ||
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| [aarch64-cpus]: https://en.wikipedia.org/wiki/Comparison_of_ARM_processors#ARMv8-A | ||
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| ## Target maintainers | ||
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| [Rust Embedded Devices Working Group Arm Team] | ||
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| [Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team | ||
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| ## Target CPU and Target Feature options | ||
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| All AArch64 processors include an FPU. The difference between the `-none` and | ||
| `-none-softfloat` targets is whether the FPU is used for passing function arguments. | ||
| You may prefer the `-softfloat` target when writing a kernel or interfacing with | ||
| pre-compiled binaries that use the soft-float ABI. | ||
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| When using the hardfloat targets, the minimum floating-point features assumed | ||
| are those of the `fp-armv8`, which excludes NEON SIMD support. If your | ||
| processor supports a different set of floating-point features than the default | ||
| expectations of `fp-armv8`, then these should also be enabled or disabled as | ||
| needed with `-C target-feature=(+/-)`. It is also possible to tell Rust (or | ||
| LLVM) that you have a specific model of Arm processor, using the | ||
| [`-Ctarget-cpu`][target-cpu] option. Doing so may change the default set of | ||
| target-features enabled. | ||
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| [target-cpu]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-cpu | ||
| [target-feature]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-feature | ||
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| ## Requirements | ||
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| These targets are cross-compiled and use static linking. | ||
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| By default, the `lld` linker included with Rust will be used; however, you may | ||
| want to use the GNU linker instead. This can be obtained for Windows/Mac/Linux | ||
| from the [Arm Developer Website][arm-gnu-toolchain], or possibly from your OS's | ||
| package manager. To use it, add the following to your `.cargo/config.toml`: | ||
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| ```toml | ||
| [target.aarch64-unknown-none] | ||
| linker = "aarch64-none-elf-ld" | ||
| ``` | ||
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| The GNU linker can also be used by specifying `aarch64-none-elf-gcc` as the | ||
| linker. This is needed when using GCC's link time optimization. | ||
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| These targets don't provide a linker script, so you'll need to bring your own | ||
| according to the specific device you are using. Pass | ||
| `-Clink-arg=-Tyour_script.ld` as a rustc argument to make the linker use | ||
| `your_script.ld` during linking. | ||
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| [arm-gnu-toolchain]: https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain | ||
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| ## Cross-compilation toolchains and C code | ||
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| This target supports C code compiled with the `aarch64-none-elf` target | ||
| triple and a suitable `-march` or `-mcpu` flag. | ||
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| ## Start-up and Low-Level Code | ||
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| The [Rust Embedded Devices Working Group Arm Team] maintain the | ||
| [`aarch64-cpu`] crate, which may be useful for writing bare-metal code using | ||
| this target. | ||
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| The *TrustedFirmware* group also maintain [Rust crates for this | ||
| target](https://github.com/ArmFirmwareCrates). | ||
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| [`aarch64-cpu`]: https://docs.rs/aarch64-cpu | ||
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There was a problem hiding this comment. I'm not really sure how the maintainers feel about endorsing third-party crates like this. I think this section could just be dropped and, if you really want to have some start-up code, replaced with a tiny linker script + assembly + Rust entrypoint example when e.g. booting with the Linux boot protocol. There was a problem hiding this comment. For many targets the code required is more than can fit into a target doc, and often involves multiple files that would be tedious and error prone to copy-paste into a new project. ArmFirmwareCrates is from Arm themselves, so it seemed legit to refer to it. But I can take it out. I personally find it pretty hard to get started with many of these targets so I think giving people links to code that works and runs is very useful. I’m happy to not have it here, but I don’t know where else it would go. There was a problem hiding this comment. For a target, if the maintainers think it worthwhile to recommend a crate that deals with the special needs of that target, then we generally do not impede such. Often, external software is required anyways for a target, e.g. specialty linkers or compilers or headers or... whatever. If quite a lot of such supplemental material is needed, it may come as an advisory against maintaining the target at all, but this doesn't seem to rise to such a threshold. |
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| # `armebv7r-none-eabi` and `armebv7r-none-eabihf` | ||
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| * **Tier: 2** | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
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| Bare-metal target for CPUs in the Armv7-R architecture family running in Big | ||
| Endian mode. These processors support dual ARM/Thumb mode, with ARM mode as | ||
| the default. | ||
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| **NOTE:** You should almost always prefer the [little-endian | ||
| versions](armv7r-none-eabi.md) of these target. Big Endian Arm systems are | ||
| highly unusual. | ||
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| Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r]. | ||
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| See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all | ||
| `arm-none-eabi` targets. | ||
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| [cortex-r]: https://en.wikipedia.org/wiki/ARM_Cortex-R | ||
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| ## Target maintainers | ||
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| [@chrisnc](https://github.com/chrisnc) | ||
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| ## Requirements | ||
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| Note that some variants of the Cortex-R have both big-endian instructions and | ||
| data. This configuration is known as BE-32, while data-only big-endianness is | ||
| known as BE-8. To build programs for BE-32 processors, the GNU linker must be | ||
| used with the `-mbe32` option. See [ARM Cortex-R Series Programmer's Guide: | ||
| Endianness][endianness] for more details about different endian modes. | ||
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| When using the hardfloat targets, the minimum floating-point features assumed | ||
| are those of the `vfpv3-d16`, which includes single- and double-precision, with | ||
| 16 double-precision registers. This floating-point unit appears in Cortex-R4F | ||
| and Cortex-R5F processors. See [VFP in the Cortex-R processors][vfp] | ||
| for more details on the possible FPU variants. | ||
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| If your processor supports a different set of floating-point features than the | ||
| default expectations of `vfpv3-d16`, then these should also be enabled or | ||
| disabled as needed with `-C target-feature=(+/-)`. | ||
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| [endianness]: https://developer.arm.com/documentation/den0042/a/Coding-for-Cortex-R-Processors/Endianness | ||
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| [vfp]: https://developer.arm.com/documentation/den0042/a/Floating-Point/Floating-point-basics-and-the-IEEE-754-standard/VFP-in-the-Cortex-R-processors | ||
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| ## Start-up and Low-Level Code | ||
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| The [Rust Embedded Devices Working Group Arm Team] maintain the [`cortex-ar`] | ||
| and [`cortex-r-rt`] crates, which may be useful for writing bare-metal code | ||
| using this target. Those crates include several examples which run in QEMU and | ||
| build using these targets. | ||
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| [`cortex-ar`]: https://docs.rs/cortex-ar | ||
| [`cortex-r-rt`]: https://docs.rs/cortex-r-rt |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,70 @@ | ||
| # `armv7a-none-eabi` and `armv7a-none-eabihf` | ||
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| * **Tier: 2** for `armv7a-none-eabi` | ||
| * **Tier: 3** for `armv7a-none-eabihf` | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
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| Bare-metal target for CPUs in the Armv7-A architecture family, supporting | ||
| dual ARM/Thumb mode, with ARM mode as the default. | ||
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| Note, this is for processors running in AArch32 mode. For the AArch64 mode | ||
| added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead. | ||
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| Processors in this family include the [Arm Cortex-A5, 8, 32, etc][cortex-a]. | ||
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| See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all | ||
| `arm-none-eabi` targets. | ||
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| [cortex-a]: https://en.wikipedia.org/wiki/ARM_Cortex-A | ||
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| ## Target maintainers | ||
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| [Rust Embedded Devices Working Group Arm Team] | ||
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| [Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team | ||
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| ## Requirements | ||
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| Almost all Armv7-A processors include an FPU (a VFPv3 or a VFPv4). The | ||
| difference between the `-eabi` and `-eabihf` targets is whether the FPU is | ||
| used for passing function arguments. You may prefer the `-eabi` soft-float | ||
| target when the processor does not have a floating point unit or the compiled | ||
| code should not use the floating point unit. | ||
|
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| When using the hardfloat targets, the minimum floating-point features assumed | ||
| are those of the VFPv3-D16, which includes single- and double-precision, with | ||
| 16 double-precision registers. This floating-point unit appears in Cortex-A8 | ||
| and Cortex-A9 processors. See [VFP in the Cortex-A processors][vfp] for more | ||
| details on the possible FPU variants. | ||
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| If your processor supports a different set of floating-point features than the | ||
| default expectations of VFPv3-D16, then these should also be enabled or | ||
| disabled as needed with `-C target-feature=(+/-)`. | ||
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| In general, the following four combinations are possible: | ||
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| - VFPv3-D16, target feature `+vfp3` and `-d32` | ||
| - VFPv3-D32, target feature `+vfp3` and `+d32` | ||
| - VFPv4-D16, target feature `+vfp4` and `-d32` | ||
| - VFPv4-D32, target feature `+vfp4` and `+d32` | ||
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| An Armv7-A processor may optionally include a NEON hardware unit which | ||
| provides Single Instruction Multiple Data (SIMD) operations. The | ||
| implementation of this unit implies VFPv3-D32. The target feature `+neon` may | ||
| be added to inform the compiler about the availability of NEON. | ||
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| You can refer to the [arm-none-eabi](arm-none-eabi.md) documentation for a | ||
| generic guide on target feature and target CPU specification and how to enable | ||
| and disable them via `.cargo/config.toml` file. | ||
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| [vfp]: https://developer.arm.com/documentation/den0013/0400/Floating-Point/Floating-point-basics-and-the-IEEE-754-standard/ARM-VFP | ||
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| ## Start-up and Low-Level Code | ||
|
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| The [Rust Embedded Devices Working Group Arm Team] maintain the [`cortex-ar`] | ||
| and [`cortex-a-rt`] crates, which may be useful for writing bare-metal code | ||
| using this target. The [`cortex-ar` repository](https://github.com/rust-embedded/cortex-ar) | ||
| includes several examples which run in QEMU and build using these targets. | ||
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| [`cortex-ar`]: https://docs.rs/cortex-ar | ||
| [`cortex-a-rt`]: https://docs.rs/cortex-a-rt |
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