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[BOLT] Update skipRelocation for aarch64
The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, add the new case to the skipRelocation for aarch64. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Differential Revision: https://reviews.llvm.org/D123334
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-12
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4 files changed

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‎bolt/lib/Core/Relocation.cpp‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -168,16 +168,17 @@ bool skipRelocationProcessX86(uint64_t Type, uint64_t Contents) {
168168
bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
169169
auto IsMov = [](uint64_t Contents) -> bool {
170170
// The bits 28-23 are 0b100101
171-
if ((Contents & 0x1f800000) == 0x12800000)
172-
return true;
173-
return false;
171+
return (Contents & 0x1f800000) == 0x12800000;
174172
};
175173

176174
auto IsB = [](uint64_t Contents) -> bool {
177175
// The bits 31-26 are 0b000101
178-
if ((Contents & 0xfc000000) == 0x14000000)
179-
return true;
180-
return false;
176+
return (Contents & 0xfc000000) == 0x14000000;
177+
};
178+
179+
auto IsAdr = [](uint64_t Contents) -> bool {
180+
// The bits 31-24 are 0b0xx10000
181+
return (Contents & 0x9f000000) == 0x10000000;
181182
};
182183

183184
auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
@@ -205,7 +206,7 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
205206
}
206207
}
207208

208-
// The ld might replace load/store instruction with jump and
209+
// The linker might replace load/store instruction with jump and
209210
// veneer due to errata 843419
210211
// https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
211212
// Thus load/store relocations for these instructions must be ignored
@@ -223,6 +224,18 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
223224
}
224225
}
225226

227+
// The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
228+
switch (Type) {
229+
default:
230+
break;
231+
case ELF::R_AARCH64_ADR_PREL_PG_HI21:
232+
case ELF::R_AARCH64_ADD_ABS_LO12_NC:
233+
case ELF::R_AARCH64_ADR_GOT_PAGE:
234+
case ELF::R_AARCH64_LD64_GOT_LO12_NC:
235+
if (IsAdr(Contents))
236+
return true;
237+
}
238+
226239
return false;
227240
}
228241

‎bolt/test/AArch64/Inputs/skip-got-rel.yaml‎

Lines changed: 172 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,172 @@
1+
--- !ELF
2+
FileHeader:
3+
Class: ELFCLASS64
4+
Data: ELFDATA2LSB
5+
Type: ET_DYN
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Machine: EM_AARCH64
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Entry: 0x10364
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ProgramHeaders:
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- Type: PT_PHDR
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Flags: [ PF_R ]
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VAddr: 0x40
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Align: 0x8
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- Type: PT_INTERP
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Flags: [ PF_R ]
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FirstSec: .interp
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LastSec: .interp
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VAddr: 0x238
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- Type: PT_LOAD
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Flags: [ PF_R ]
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FirstSec: .interp
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LastSec: .dynamic
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Align: 0x10000
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- Type: PT_LOAD
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Flags: [ PF_X, PF_R ]
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FirstSec: .text
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LastSec: .text
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VAddr: 0x10348
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Align: 0x10000
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- Type: PT_LOAD
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Flags: [ PF_W, PF_R ]
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LastSec: .got
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VAddr: 0x20388
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Type: R_AARCH64_LD64_GOT_LO12_NC
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...

‎bolt/test/AArch64/skip-got-rel.test‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
// This test checks that the binary with relaxed ADRP+LDR instructions is
2+
// processed normally with BOLT and the ADR instruction address is recognized
3+
// normally.
4+
5+
RUN: yaml2obj %p/Inputs/skip-got-rel.yaml &> %t.exe
6+
RUN: llvm-bolt %t.exe -o /dev/null -print-cfg -print-only=_start | FileCheck %s
7+
8+
CHECK: adr x0, foo2

‎bolt/test/runtime/plt-lld.test‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,16 @@
11
// This test checks that the pointers to PLT are properly updated.
22
// The test is using lld linker.
33

4-
// RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
5-
// RUN: -o %t.lld.exe -Wl,-q
6-
// RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
7-
// RUN: %t.lld.bolt.exe | FileCheck %s
4+
// Non-PIE:
5+
RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
6+
RUN: -o %t.lld.exe -Wl,-q
7+
RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
8+
RUN: %t.lld.bolt.exe | FileCheck %s
89

9-
// CHECK: Test completed
10+
// PIE:
11+
RUN: %clang %cflags -fPIC -pie %p/../Inputs/plt.c -fuse-ld=lld \
12+
RUN: -o %t.lld.pie.exe -Wl,-q
13+
RUN: llvm-bolt %t.lld.pie.exe -o %t.lld.bolt.pie.exe -use-old-text=0 -lite=0
14+
RUN: %t.lld.bolt.pie.exe | FileCheck %s
15+
16+
CHECK: Test completed

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