- day1 - Basic Gates
- day2 - Mux
- day3 - Full Subtractor
- day4 - Encoder
- day5 - D FlipFlop
- day6 - 8 bit Counter
- day7 - Binary to onehot encoder
- day8 - LFSR
- day9 - Custom Counter
- day10 - Mux using case
- day11 - JK FlipFlop
- day12 - T FlipFlop
- day13 - Positive egde detection
- day14 - Priority encoder
- day15 - Barrel shifter
- day16 - Signed Magnitude adder
- day17 - Free Running Counter
- day18 - Mod-m Counter
- day19 - Edge Detector with Moore
- day20 - Edge Detector with Mealy
- day21 - 2 to 4 binary decoder
- day22 - Dual (Rising & Falling) edge detector
- day23 - alu
- day24 - Sequence Detector 1101 mealy nonoverlap
- day25 - Sequence Detector 1101 mealy overlap
- day26 - Sequence Detector 1101 moore nonoverlap
- day27 - Sequence Detector 1101 moore overlap
- day28 - Binary to Gray Converter
- day29 - Sequential Multiplier
- day30 - Single port RAM
- day31 - Up down counter
- day32 - Parallel in parallel out (PIPO)
- day33 - Parallel in serial out (PISO)
- day34 - Serial in parallel out (SIPO)
-
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100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
snbk001/100DaysofRTL
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100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
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