VeeR EH1 core

How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design

体系结构研讨 + ysyx高阶大纲 (WIP

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

riscv32i-cpu

An open-source microcontroller system based on RISC-V

32-bit Superscalar RISC-V CPU

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor

Teaching-focused digital circuit simulator

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

Simple risc-v emulator, able to run linux, written in C.

Random instruction generator for RISC-V processor verification

The book "Performance Analysis and Tuning on Modern CPU"

Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920

RV64GC Linux Capable RISC-V Core

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

OpenTitan: Open source silicon root of trust

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support