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According to the manual:

The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write.

Switching the system clock before that can cause problems since some clock domains have maximum allowed values.

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@therealprof therealprof left a comment

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Excellent, thanks.

@therealprof therealprof merged commit ddccb4f into stm32-rs:master Apr 2, 2020
@thalesfragoso thalesfragoso deleted the wait-pre branch July 19, 2020 02:54
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2 participants