@@ -3054,33 +3054,6 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
30543054 return SGPRReg;
30553055}
30563056
3057- void SIInstrInfo::reserveIndirectRegisters (BitVector &Reserved,
3058- const MachineFunction &MF) const {
3059- int End = getIndirectIndexEnd (MF);
3060- int Begin = getIndirectIndexBegin (MF);
3061-
3062- if (End == -1 )
3063- return ;
3064-
3065- for (int Index = Begin; Index <= End; ++Index)
3066- Reserved.set (AMDGPU::VGPR_32RegClass.getRegister (Index));
3067-
3068- for (int Index = std::max (0 , Begin - 1 ); Index <= End; ++Index)
3069- Reserved.set (AMDGPU::VReg_64RegClass.getRegister (Index));
3070-
3071- for (int Index = std::max (0 , Begin - 2 ); Index <= End; ++Index)
3072- Reserved.set (AMDGPU::VReg_96RegClass.getRegister (Index));
3073-
3074- for (int Index = std::max (0 , Begin - 3 ); Index <= End; ++Index)
3075- Reserved.set (AMDGPU::VReg_128RegClass.getRegister (Index));
3076-
3077- for (int Index = std::max (0 , Begin - 7 ); Index <= End; ++Index)
3078- Reserved.set (AMDGPU::VReg_256RegClass.getRegister (Index));
3079-
3080- for (int Index = std::max (0 , Begin - 15 ); Index <= End; ++Index)
3081- Reserved.set (AMDGPU::VReg_512RegClass.getRegister (Index));
3082- }
3083-
30843057MachineOperand *SIInstrInfo::getNamedOperand (MachineInstr &MI,
30853058 unsigned OperandName) const {
30863059 int Idx = AMDGPU::getNamedOperandIdx (MI.getOpcode (), OperandName);
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