[x86] add tests for FP->int->FP with different FP types; NFC

Author: rotateright

llvm/test/CodeGen/X86/ftrunc.ll

@@ -298,6 +298,78 @@ define double @trunc_signed32_f64_nsz(double %x) #0 {
   ret double %r
 }
 
+define double @trunc_f32_signed32_f64_no_fast_math(float %x) {
+; SSE-LABEL: trunc_f32_signed32_f64_no_fast_math:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttss2si %xmm0, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2sd %eax, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: trunc_f32_signed32_f64_no_fast_math:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vcvttss2si %xmm0, %eax
+; AVX1-NEXT:    vcvtsi2sd %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi float %x to i32
+  %r = sitofp i32 %i to double
+  ret double %r
+}
+
+define double @trunc_f32_signed32_f64_nsz(float %x) #0 {
+; SSE-LABEL: trunc_f32_signed32_f64_nsz:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttss2si %xmm0, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2sd %eax, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: trunc_f32_signed32_f64_nsz:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vcvttss2si %xmm0, %eax
+; AVX1-NEXT:    vcvtsi2sd %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi float %x to i32
+  %r = sitofp i32 %i to double
+  ret double %r
+}
+
+define float @trunc_f64_signed32_f32_no_fast_math(double %x) {
+; SSE-LABEL: trunc_f64_signed32_f32_no_fast_math:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttsd2si %xmm0, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2ss %eax, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: trunc_f64_signed32_f32_no_fast_math:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vcvttsd2si %xmm0, %eax
+; AVX1-NEXT:    vcvtsi2ss %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi double %x to i32
+  %r = sitofp i32 %i to float
+  ret float %r
+}
+
+define float @trunc_f64_signed32_f32_nsz(double %x) #0 {
+; SSE-LABEL: trunc_f64_signed32_f32_nsz:
+; SSE:       # %bb.0:
+; SSE-NEXT:    cvttsd2si %xmm0, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2ss %eax, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX1-LABEL: trunc_f64_signed32_f32_nsz:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vcvttsd2si %xmm0, %eax
+; AVX1-NEXT:    vcvtsi2ss %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi double %x to i32
+  %r = sitofp i32 %i to float
+  ret float %r
+}
+
 define double @trunc_signed_f64_no_fast_math(double %x) {
 ; SSE-LABEL: trunc_signed_f64_no_fast_math:
 ; SSE:       # %bb.0: