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[GlobalISel] Fix invalid combine of unmerge(merge) with intermediate cast
Summary: The combine for unmerge(cast(merge)) is only valid for vectors, but was missing a corresponding check. Add a check that the operands are vectors to avoid an invalid combine. Without this check, the combiner would emit incorrect code for scalars and pointers because the artifact cast (trunc/ext) only affects bits at the end of the type, while this combine assumes that the casted bits appear between meaningful bits. This also uncovered a segmentation fault in the AMDGPU InstructionSelector. The tests triggering this bug have been moved to their own file and a check for the segmentation fault has been added. Reviewers: arsenm, dsanders, aemerson, paquette, aditya_nandakumar Reviewed By: arsenm Subscribers: tpr, jvesely, wdng, nhaehnle, rovka, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78191
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9 files changed

+1175
-995
lines changed

9 files changed

+1175
-995
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -364,7 +364,7 @@ class LegalizationArtifactCombiner {
364364
// That is not done yet.
365365
if (ConvertOp == 0)
366366
return true;
367-
return !DestTy.isVector();
367+
return !DestTy.isVector() && OpTy.isVector();
368368
case TargetOpcode::G_CONCAT_VECTORS: {
369369
if (ConvertOp == 0)
370370
return true;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir‎

Lines changed: 70 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -910,10 +910,10 @@ body: |
910910
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
911911
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
912912
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
913-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
914-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
915-
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
916-
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s32), implicit [[TRUNC1]](s32), implicit [[TRUNC2]](s32)
913+
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64)
914+
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s192)
915+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
916+
; CHECK: S_ENDPGM 0, implicit [[UV]](s32), implicit [[UV1]](s32), implicit [[UV2]](s32)
917917
%0:_(s64) = COPY $vgpr0_vgpr1
918918
%1:_(s64) = COPY $vgpr2_vgpr3
919919
%2:_(s64) = COPY $vgpr4_vgpr5
@@ -933,16 +933,20 @@ body: |
933933
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
934934
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
935935
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
936-
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
937-
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
938-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
939-
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
940-
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
941-
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
942-
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
943-
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV4]](s32)
944-
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
945-
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16), implicit [[TRUNC5]](s16)
936+
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64)
937+
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s192)
938+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
939+
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
940+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
941+
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
942+
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
943+
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
944+
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
945+
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
946+
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
947+
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
948+
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
949+
; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16), implicit [[TRUNC5]](s16), implicit [[TRUNC6]](s16)
946950
%0:_(s64) = COPY $vgpr0_vgpr1
947951
%1:_(s64) = COPY $vgpr2_vgpr3
948952
%2:_(s64) = COPY $vgpr4_vgpr5
@@ -968,11 +972,15 @@ body: |
968972
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
969973
; CHECK: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
970974
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
971-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
972-
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
973-
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
974-
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
975-
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
975+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
976+
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
977+
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
978+
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
979+
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
980+
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
981+
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
982+
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
983+
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
976984
; CHECK: S_ENDPGM 0, implicit [[MV]](s192), implicit [[MV1]](s96), implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16), implicit [[TRUNC5]](s16)
977985
%0:_(s32) = COPY $vgpr0
978986
%1:_(s32) = COPY $vgpr1
@@ -986,3 +994,46 @@ body: |
986994
S_ENDPGM 0, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13
987995
988996
...
997+
998+
---
999+
name: test_unmerge_values_s64_anyext_s128_of_merge_values_s64
1000+
body: |
1001+
bb.0:
1002+
; CHECK-LABEL: name: test_unmerge_values_s64_anyext_s128_of_merge_values_s64
1003+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
1004+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
1005+
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
1006+
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
1007+
; CHECK: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64)
1008+
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV1]](s128)
1009+
; CHECK: $vgpr0_vgpr1 = COPY [[UV]](s64)
1010+
; CHECK: $vgpr2_vgpr3 = COPY [[UV1]](s64)
1011+
%0:_(s32) = COPY $vgpr0
1012+
%1:_(s32) = COPY $vgpr1
1013+
%2:_(s64) = G_MERGE_VALUES %0, %1
1014+
%3:_(s128) = G_ANYEXT %2
1015+
%4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %3
1016+
$vgpr0_vgpr1 = COPY %4
1017+
$vgpr2_vgpr3 = COPY %5
1018+
1019+
...
1020+
1021+
---
1022+
name: test_unmerge_values_s32_trunc_s64_of_merge_values_s128
1023+
body: |
1024+
bb.0:
1025+
; CHECK-LABEL: name: test_unmerge_values_s32_trunc_s64_of_merge_values_s128
1026+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
1027+
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
1028+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
1029+
; CHECK: $vgpr0 = COPY [[UV]](s32)
1030+
; CHECK: $vgpr1 = COPY [[UV1]](s32)
1031+
%0:_(s64) = COPY $vgpr0_vgpr1
1032+
%1:_(s64) = COPY $vgpr2_vgpr3
1033+
%2:_(s128) = G_MERGE_VALUES %0, %1
1034+
%3:_(s64) = G_TRUNC %2
1035+
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3
1036+
$vgpr0 = COPY %4
1037+
$vgpr1 = COPY %5
1038+
1039+
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
; RUN: not --crash llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s
2+
; RUN: not --crash llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s
3+
4+
define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind {
5+
%trunc = trunc i32 %arg0 to i24
6+
%val = bitcast i24 %trunc to <3 x i8>
7+
%cvt = uitofp <3 x i8> %val to <3 x float>
8+
ret <3 x float> %cvt
9+
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll‎

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -191,40 +191,6 @@ define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {
191191
ret <2 x float> %cvt
192192
}
193193

194-
define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind {
195-
; SI-LABEL: v_uitofp_v3i8_to_v3f32:
196-
; SI: ; %bb.0:
197-
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
198-
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0
199-
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
200-
; SI-NEXT: s_movk_i32 s4, 0xff
201-
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
202-
; SI-NEXT: v_and_b32_e32 v0, s4, v0
203-
; SI-NEXT: v_and_b32_e32 v1, s4, v1
204-
; SI-NEXT: v_and_b32_e32 v2, s4, v2
205-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
206-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
207-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
208-
; SI-NEXT: s_setpc_b64 s[30:31]
209-
;
210-
; VI-LABEL: v_uitofp_v3i8_to_v3f32:
211-
; VI: ; %bb.0:
212-
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
213-
; VI-NEXT: s_movk_i32 s4, 0xff
214-
; VI-NEXT: v_mov_b32_e32 v2, s4
215-
; VI-NEXT: v_and_b32_sdwa v1, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
216-
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
217-
; VI-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
218-
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
219-
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
220-
; VI-NEXT: v_mov_b32_e32 v0, v3
221-
; VI-NEXT: s_setpc_b64 s[30:31]
222-
%trunc = trunc i32 %arg0 to i24
223-
%val = bitcast i24 %trunc to <3 x i8>
224-
%cvt = uitofp <3 x i8> %val to <3 x float>
225-
ret <3 x float> %cvt
226-
}
227-
228194
define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind {
229195
; SI-LABEL: v_uitofp_v4i8_to_v4f32:
230196
; SI: ; %bb.0:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir‎

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -292,23 +292,25 @@ body: |
292292
; CHECK-LABEL: name: test_bitcast_s24_to_v3s8
293293
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
294294
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
295+
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
295296
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
296-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
297-
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
298-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
297+
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64)
298+
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
299+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
300+
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
299301
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
300-
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
302+
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
301303
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
302304
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
303305
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
304306
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
305-
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
307+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
306308
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
307-
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
308-
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
309-
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
310-
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
311-
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
309+
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
310+
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
311+
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
312+
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
313+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
312314
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
313315
%0:_(s32) = COPY $vgpr0
314316
%1:_(s24) = G_TRUNC %0
@@ -326,21 +328,24 @@ body: |
326328
; CHECK-LABEL: name: test_bitcast_s48_to_v3s16
327329
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
328330
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
331+
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
329332
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
330-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
331-
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
333+
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64)
334+
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
335+
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
332336
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
333-
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
334-
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
337+
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
338+
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
335339
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
336-
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
337-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
338-
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
339-
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
340+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
341+
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
342+
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
343+
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
340344
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
341345
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
342346
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
343-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]]
347+
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
348+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
344349
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
345350
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
346351
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -349,10 +354,10 @@ body: |
349354
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
350355
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
351356
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
352-
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
353-
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
357+
; CHECK: [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
358+
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
354359
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
355-
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
360+
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
356361
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
357362
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
358363
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)

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