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Update the SSR Tile IDs to be u16s instead to better match LPP.

@jbangelo jbangelo force-pushed the jbangelo/fixup-ssr-tile-id branch from 8b5937b to 375153b Compare August 25, 2020 21:26
@jbangelo jbangelo requested review from benjamin0 and ljbade August 25, 2020 22:24
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ljbade commented Aug 25, 2020

@jbangelo is it worth going to full 32 bits? that would then match SIP. Unless we want to drop SIP to 16 bits, that way we won't have to worry about overflow when translating

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I don't see much need for a full 32-bits here, 8 bits is a bit small for long term growth but 16 bits would seem to give us more than enough room. I'm not sure if there's a real need for the addition 4 bytes in the message if they probably aren't going to be used.

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ljbade commented Aug 26, 2020

@jbangelo fair enough

do you mind fixing up this bit of the SSR docs I just noticed was wrong for STECSatElement.stec_coeff
units: C00 = 0.05 TECU, C01/C10 = 0.02 TECU/deg, C11 0.02 TECU/deg^2

@jbangelo jbangelo force-pushed the jbangelo/fixup-ssr-tile-id branch from 375153b to b123db5 Compare August 26, 2020 18:36
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Done @ljbade

@jbangelo jbangelo merged commit a078808 into master Aug 27, 2020
@jbangelo jbangelo deleted the jbangelo/fixup-ssr-tile-id branch August 27, 2020 01:13
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3 participants