Fix incorrect nested trap handling in RISC-V HAL #43
+37
−25
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This commit removes manual mstatus bit manipulation and allows hardware to manage interrupt enable state per RISC-V Privileged Spec §3.1.6.1. The original code manually reconstructed mstatus.MIE from mstatus.MPIE during context save, which violated the RISC-V specification. Hardware automatically manages the MIE/MPIE stack during trap entry (mpie <- mie, mie <- 0) and MRET (mie <- mpie, mpie <- 1), so manual intervention is unnecessary and causes bugs with nested trap handling. This fix ensures spec-compliant behavior, resolves nested interrupt issues, and improves code clarity with 78% reduction in context save instructions. Close #16
Linmo CI Test ResultsOverall Status: ✅ passed Toolchain Results
Application Tests
Functional Test Details
Report generated from |
![cubic-dev-ai[bot]](https://avatars.githubusercontent.com/in/1082092?s=60&v=4){kind=small}
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This commit removes manual mstatus bit manipulation and allows hardware to manage interrupt enable state per RISC-V Privileged Spec §3.1.6.1.
The original code manually reconstructed mstatus.MIE from mstatus.MPIE during context save, which violated the RISC-V specification. Hardware automatically manages the MIE/MPIE stack during trap entry (mpie <- mie, mie <- 0) and MRET (mie <- mpie, mpie <- 1), so manual intervention is unnecessary and causes bugs with nested trap handling.
This fix ensures spec-compliant behavior, resolves nested interrupt issues, and improves code clarity with 78% reduction in context save instructions.
Close #16
Summary by cubic
Fixes incorrect nested trap handling in the RISC-V HAL by relying on hardware to manage MIE/MPIE per §3.1.6.1. Restores spec-compliant interrupt behavior and reduces context-save code size.
Bug Fixes
Refactors
Written for commit 275bc84. Summary will update automatically on new commits.