Implement MMU translation caching with 2-way load

[jserv]

This adds TLB to cache virtual-to-physical address translations:

• cache_fetch: 1-entry direct-mapped for instruction fetch
• cache_load: 2-entry direct-mapped with hash-based indexing
• cache_store: 1-entry direct-mapped for data stores

Cache invalidation handled at all necessary points: SATP writes, fence instructions, mode switches, and trap entry/exit.

Optional statistics support via MMU_CACHE_STATS compile flag shows ~96% fetch, ~69% load, and ~84% store hit rates during kernel boot.

---

Summary by cubic

Add a small TLB for MMU translations: 1-entry caches for fetch/store and a 2-way cache for loads. This cuts page-table walks and speeds up memory access, with optional per-hart hit/miss stats.

• New Features

  • 1-entry direct-mapped fetch and store translation caches.
  • 2-way set-associative load translation cache (indexed by VPN bit 0).
  • Central mmu_invalidate clears all caches; RFENCE now calls it.
  • MMU_CACHE_STATS flag: per-hart hit/miss counters and a summary printout; run exits after 15s to dump stats.
  • Observed hit rates: ~96% fetch, ~69% load, ~84% store during kernel boot.

• Bug Fixes

  • LR/SC reservations now track physical addresses to avoid alias issues.